Specifications

dsPIC33F Family Reference Manual
DS70183A-page 16-42 © 2006 Microchip Technology Inc.
Table 16-4: Converting Three Inputs, Four Times and Four Inputs, One Time per DMA Interrupt
CONTROL BITS OPERATION SEQUENCE
Sequence Select Sample MUX A Inputs:
SMPI<3:0> = 0011 , AMODE = 00 , DMAxCNT = 15 AN4 -> CH0, AN0 -> CH1, AN1 -> CH2, AN2 -> CH3
Scan 4 inputs, Interrupt on 16th conversion Convert CH0, write ADC1BUF0, and generate DMA Request
CHPS<1:0> = 1x Convert CH1, write ADC1BUF0, and generate DMA Request
Sample Channels CH0, CH1, CH2, CH3 Convert CH2, write ADC1BUF0, and generate DMA Request
SIMSAM = 1 Convert CH3, write ADC1BUF0, and generate DMA Request
Sample all channels simultaneously Sample MUX A Inputs:
BUFM = 0 AN5 -> CH0, AN0 -> CH1, AN1 -> CH2, AN2 -> CH3
Single 16-word result buffer Convert CH0, write ADC1BUF0, and generate DMA Request
ALTS = 0 Convert CH1, write ADC1BUF0, and generate DMA Request
Always use MUX A input select Convert CH2, write ADC1BUF0, and generate DMA Request
MUX A Input Select Convert CH3, write ADC1BUF0, and generate DMA Request
CH0SA<3:0> = n/a Sample MUX A Inputs:
Override by CSCNA AN6 -> CH0, AN0 -> CH1, AN1 -> CH2, AN2 -> CH3
CH0NA = 0 Convert CH0, write ADC1BUF0, and generate DMA Request
Select V
REF- for CH0- input Convert CH1, write ADC1BUF0, and generate DMA Request
CSCNA = 1 Convert CH2,write ADC1BUF0, and generate DMA Request
Scan CH0+ Inputs Convert CH3, write ADC1BUF0, and generate DMA Request
CSSL<15:0> = 0000 0000 1111 0000 Sample MUX A Inputs:
Scan AN4, AN5, AN6, AN7 AN7 -> CH0, AN0 -> CH1, AN1 -> CH2, AN2 -> CH3
CH123SA = 0 Convert CH0, write ADC1BUF0, and generate DMA Request
CH1+ = AN0, CH2+ = AN1, CH3+ = AN2 Convert CH1, write ADC1BUF0, and generate DMA Request
CH123NA<1:0> = 0x Convert CH2, write ADC1BUF0, and generate DMA Request
CH1-, CH2-, CH3- = V
REF- Convert CH3, write ADC1BUF0, and generate DMA Request
MUX B Input Select Interrupt
CH0SB<3:0> = n/a Repeat
Channel CH0+ input unused
CH0NB = n/a
Channel CH0- input unused
CH123SB = n/a
Channel CH1, CH2, CH3 + input unused
CH123NB<1:0> = n/a
Channel CH1, CH2, CH3 – input unused
DMA Buffer @
1st DMA Interrupt
DMA Buffer @
2nd DMA Interrupt
AN4 Sample 1 AN4 Sample 2
AN0 Sample 1 AN0 Sample 5
AN1 Sample 1 AN1 Sample 5
AN2 Sample 1 AN2 Sample 5
AN5 Sample 1 AN5 Sample 2
AN0 Sample 2 AN0 Sample 6
AN1 Sample 2 AN1 Sample 6
AN2 Sample 2 AN2 Sample 6
AN6 Sample 1 AN6 Sample 2
AN0 Sample 3 AN0 Sample 7
AN1 Sample 3 AN1 Sample 7
AN2 Sample 3 AN2 Sample 7
AN7 Sample 1 AN7 Sample 2
AN0 Sample 4 AN0 Sample 8
AN1 Sample 4 AN1 Sample 8
AN2 Sample 4 AN2 Sample 8