Specifications

© 2006 Microchip Technology Inc. DS70183A-page 16-37
Section 16. Analog-to-Digital Converter (ADC)
A
D
C
16
16.14 CONVERSION SEQUENCE EXAMPLES
The following configuration examples show the A/D operation in different sampling and buffering
configurations. In each example, setting the ASAM bit starts automatic sampling. A conversion
trigger ends sampling and starts conversion.
16.14.1 Sampling and Converting a Single Channel Multiple Times
Figure 16-17 and Table 16-2 illustrate a basic configuration of the ADC. In this case, one ADC
input, AN0, is sampled by one Sample/Hold channel, CH0, and converted. The results are stored
in the user-configured DMA buffer, illustrated as Buffer(0) through Buffer(15). This process
repeats 16 times until the buffer is full and then the ADC module generates an interrupt. The
entire process then repeats.
The CHPS bits specify that only Sample/Hold CH0 is active. With ALTS clear, only the MUX A
inputs are active. The CH0SA bits and CH0NA bit are specified (AN0-V
REF-) as the input to the
Sample/Hold channel. All other input selection bits are not used.
Figure 16-17: Converting One Channel 16 Times/Interrupt
ADC Clock
SAMP
Buffer[0]
TSAMP
TCONV
BSET AD1CON1,ASAM
Instruction Execution
Buffer[1]
DONE
Buffer[2]
Buffer[15]
Input to CH0
AN0
TSAMP
TCONV
AN0
TSAMP
TCONV
AN0
TSAMP
TCONV
AN0
AD1IF
ASAM
Conversion
Trigger