Specifications

dsPIC33F Family Reference Manual

16.12 CONTROLLING SAMPLE/CONVERSION OPERATION

The application software can poll the SAMP (AD1CON1<1>) and DONE (AD1CON1<0>) bits to

keep track of A/D operations or the ADC module can interrupt the CPU when conversions are

complete. The application software can also abort A/D operations, if necessary.

16.12.1 Monitoring Sample/Conversion Status

The SAMP and DONE bits indicate the sampling state and the conversion state of the ADC,

respectively. Generally, when the SAMP bit clears, indicating end of sampling, the DONE bit is

automatically set, indicating end of conversion. If both SAMP and DONE are ‘0’, the ADC is in

an inactive state. In some operational modes, the SAMP bit can also invoke and terminate sam-

pling.

16.12.2 Generating an ADC Interrupt

The SMPI<3:0> bits (ADxCON2<5:2>) control the generation of interrupts. The interrupt occurs

some number of sample/conversion sequences after starting sampling and re-occurs on each

equivalent number of samples. Note that the interrupts are specified in terms of samples and not

in terms of conversions or data samples in the buffer memory.

If DMA transfers are not enabled, having a non-zero SMPI<3:0> value results in overwriting the

data in the ADCxBUF0 register. For example, if SMPI<3:0> = 0011, then every 4th conversion

result can be read in the ADC Interrupt Service Routine. However, if channel scanning is

enabled, the SMPI<3:0> bits must be set to one less than the number of channels to be scanned.

Similarly, if alternate sampling is enabled, the SMPI<3:0> bits must be set to ‘0001’.

If DMA transfers are enabled, the SMPI<3:0> bit must be cleared, except when channel scanning

or alternate sampling is used. Please refer to Section 16.13 “Specifying Conversion Results

Buffering” for more details on SMPI<3:0> setup requirements.

When the SIMSAM bit (ADxCON1<3>) specifies sequential sampling, regardless of the number

of channels specified by the CHPS<1:0> bits (ADxCON2<9:8>), the ADC module samples once

for each conversion and data sample in the buffer. The value specified by the DMAxCNT register

for the DMA channel being used corresponds to the number of data samples in the buffer.

When the SIMSAM bit specifies simultaneous sampling, the number of data samples in the buffer

is related to the CHPS<1:0> bits. Algorithmically, the channels per sample (CH/S) times the num-

ber of samples results in the number of data sample entries in the buffer. To avoid loss of data in

the buffer due to overruns, the DMAxCNT register must be set to the desired buffer size.

Disabling the ADC interrupt is not done with the SMPI<3:0> bits. To disable the interrupt, clear

the ADxIE analog module interrupt enable bit.

16.12.3 Aborting Sampling

Clearing the SAMP bit while in Manual Sampling mode terminates sampling but can also start a

conversion if SSRC<2:0> = 000.

Clearing the ASAM bit while in Automatic Sampling mode does not terminate an on going

sample/convert sequence, however, sampling does not automatically resume after subsequent

conversions.

16.12.4 Aborting a Conversion

Clearing the ADON (ADxCON1<15>) bit during a conversion aborts the current conversion. The

ADC Result register pair is NOT updated with the partially completed A/D conversion sample.

That is, the corresponding ADC1BUF0 buffer location continues to contain the value of the last

completed conversion (or the last value written to the buffer).