Specifications

Section 16. Analog-to-Digital Converter (ADC)

16.11.3.7 SAMPLE TIME CONSIDERATIONS FOR AUTOMATIC

SAMPLING/CONVERSION SEQUENCES

Different sample/conversion sequences provide different available sampling times for the Sam-

ple/Hold channel to acquire the analog signal. You must ensure that the sampling time exceeds

the sampling requirements, as outlined in Section 16.15 “A/D Sampling Requirements”.

Assuming that the ADC module is set for automatic sampling and an external trigger pulse is

used as the conversion trigger, the sampling interval is a portion of the trigger pulse interval.

If the SIMSAM bit specifies simultaneous sampling, the sampling time is the trigger pulse period

less the time required to complete the specified conversions.

Equation 16-5: Available Sampling Time, Simultaneous Sampling

If the SIMSAM bit specifies sequential sampling, the sampling time is the trigger pulse period less

the time required to complete only one conversion.

Equation 16-6: Available Sampling Time, Sequential Sampling

SMP = Trigger Pulse Interval (TSEQ) - Channels per Sample (CH/S) * Conversion Time (TCONV)

SMP = TSEQ - (CH/S * TCONV)

Note 1: CH/S is specified by CHPS<1:0> bits

2: TSEQ is the trigger pulse interval time

TSMP = Trigger Pulse Interval (TSEQ) - Conversion Time (TCONV)

SMP = TSEQ - TCONV

Note: TSEQ is the trigger pulse interval time