Specifications

dsPIC33F Family Reference Manual

16.1 INTRODUCTION

The dsPIC33F family devices have up to 32 A/D input channels. These devices also have up to

two ADC modules (ADCx, where x = 1 or 2), each with its own set of Special Function Registers

(SFRs).

The 10-bit or 12-bit Operation Mode (AD12B) bit in the ADCx Control 1(ADxCON1) register

allows each of the ADC modules to be configured by the user application as either a 10-bit, 4

Sample/Hold (S/H) ADC (default configuration) or a 12-bit, 1 Sample/Hold ADC.

The 10-bit ADC configuration (AD12B = 0) has the following key features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 1.1 Msps

• Up to 32 analog input pins

• External voltage reference input pins

• Simultaneous sampling of up to four analog input pins

• Automatic Channel Scan mode

• Selectable conversion trigger source

• Selectable Buffer Fill modes

• DMA support, including Peripheral Indirect Addressing

• Four result alignment options (signed/unsigned, fractional/integer)

• Operation during CPU Sleep and Idle modes

Depending on the particular device pinout, the ADC can have up to 32 analog input pins, desig-

nated AN0 through AN31. In addition, there are two analog input pins for external voltage refer-

ence connections. These voltage reference inputs can be shared with other analog input pins.

The actual number of analog input pins and external voltage reference input configuration will

depend on the specific device. Refer to the device data sheet for further details.

The analog inputs are multiplexed to four Sample/Hold amplifiers, designated CH0-CH3. One,

two, or four of the Sample/Hold amplifiers can be enabled for acquiring input data. The analog

input multiplexers can be switched between two sets of analog inputs during conversions. Uni-

polar differential conversions are possible on all channels using certain input pins (see

Figure 16-1).

An Analog Input Scan mode can be enabled for the CH0 Sample/Hold Amplifier. A Control

The ADC is connected to a single-word result buffer. However, multiple conversion results can

be stored in a DMA RAM buffer with no CPU overhead. Each conversion result is converted to

one of four 16-bit output formats when it is read from the buffer.

The 12-bit ADC configuration (AD12B = 1) supports all the above features, except:

• In the 12-bit configuration, conversion speeds of up to 500 ksps are supported

• There is only one Sample/Hold amplifier in the 12-bit configuration, so simultaneous

sampling of multiple channels is not supported.

Note: The ADC module needs to be disabled before the AD12B bit is modified.