Specifications

© 2008-2012 Microchip Technology Inc. DS70323E-page 43-9
Section 43. High-Speed PWM
High-Speed PWM
43
Register 43-4: SEVTCMP: PWM Special Event Compare Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
SEVTCMP<4:0>
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 SEVTCMP<12:0>: Primary Special Event Compare Count Value bits
bit 2-0 Unimplemented: Read as ‘0’
Note 1: 1 LSb = 1.04 ns. Therefore, minimum SEVTCMP resolution is 8.32 ns at the fastest PWM clock divider
setting (PTCON2<2:0> = 0).
2: The Special Event Trigger is generated on a compare match with the PWM Master Time Base Counter
(PMTMR).
3: This register is used in conjunction with the PTCON<3:0> bit field.