Specifications

Section 43. High-Speed PWM

High-Speed PWM

Figure 43-41: High-Frequency PWM Chopping

The chopping function performs a logical AND operation of the PWM outputs. Because of the

finite period of the chopping clock, the resultant PWM duty cycle resolution is limited to one half

of the chop clock period.

The PWM Chop Clock Generator register (CHOP) enables the user to specify a chopping clock

frequency. The CHOP value specifies a PWM clock divide ratio. The chop clock divider operates

at the PWM clock frequency specified by the PCLKDIV<2:0> bits (PTCON2<2:0>). The

CHPCLKEN bit in the CHOP register enables the chop clock generator.

The PWMxH Output Chopping Enable bit, CHOPHEN (AUXCONx<1>), and the PWMxL Output

Chopping Enable bit, CHOPLEN (AUXCONx<0>), enable the chop clock to be applied to the

PWM outputs. The PWM Chop Clock Source Select bits, CHOPSEL<3:0> (AUXCONx<5:2>)

select the desired source for the chop clock. The default selection is the chop clock generator

controlled by the CHOP register. The CHOPSEL<3:0> bits (AUXCONx<5:2>) enable the user to

select other PWM generators as a chop clock source.

If the CHOPHEN bit (AUXCONx<1>) or the CHOPLEN bit (AUXCONx<0>) is set, the chopping

function is applied to the PWM output signals after the current-limit and Fault functions are

applied to the PWM signal. The CHPCLK signal is available for output from the module for use

as an output signal for the device.

Normally, the chopping clock frequency is higher than the PWM cycle frequency, but new

applications can use chop clock frequencies that are much lower than the PWM cycle frequency.

Figure 43-42 illustrates a low-frequency PWM chopping waveform. In this figure, another PWM

generator operating at a lower frequency chops or “blanks” the PWM signal.

Figure 43-42: Low-Frequency PWM Chopping

50 μsec

Unchopped PWM

Chopping Signal

Chopped PWM

1 μsec

Note: Not drawn to scale.

50 ms

Chopping Signal

Unchopped PWM

Chopped PWM

Note: Not drawn to scale.

1 μsec