Specifications

Section 43. High-Speed PWM

High-Speed PWM

OVRENL(IOCONx<8>) to high.

4. Disable the PWM fault by setting FLTMOD<1:0> bits (FCLCONx<1:0>) = ‘0b11.

5. Provide a delay of at least 1 PWM cycle.

6. Enable the PWM fault by setting FLTMOD<1:0> bits (FCLCONx<1:0>) =‘0b00.

7. If PWM Fault interrupt is enabled then perform the following sub-steps and then proceed

to step 8. If not then skip this step and proceed to step 8.

- a) Complete the PWM fault Interrupt Service Routine.

- b) Disable the PWM fault interrupt by clearing the FLTIEN bit (PWMCONx<12> = 0.

- c) Enable the PWM fault interrupt by setting the FLTIEN bit (PWMCONx<12>) = 1.

8. Disable the override by clearing the OVRENH (IOCONx<9>) and OVRENL (IOCONx<8>)

bits.

43.10.5 Fault Exit with PMTMR Disabled

There is a special case for exiting a Fault condition when the PWM time base is

disabled (PTEN = 0). When a fault input is programmed for Cycle-by-Cycle mode, the PWM

outputs are immediately restored to normal operation when the fault input pin is deasserted. The

PWM outputs should return to their default programmed values. When a fault input is

programmed for Latched mode, the PWM outputs are restored immediately when the fault input

pin is deasserted and the FLTSTAT bit (PWMCONx<15>) is cleared in software.

43.10.6 Fault Pin Software Control

The fault pin can be controlled manually in software. Since the fault input is shared with a GPIO

port pin, this pin can be configured as an output by clearing the corresponding TRIS bit. When

the port bit for the GPIO pin is set, the fault input will be activated.