Specifications

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dsPIC33F/PIC24H Family Reference Manual

43.10.2 Fault Interrupts

The FLTIENx bits (PWMCONx<12>) determine whether an interrupt will be generated when the

FLTx input is asserted high. The FLTDAT<1:0> bits (High/Low) (IOCONx<5:4>) supply the data

values to be assigned to the PWMxH and PWMxL pins in case of a fault.

The PWM Fault state is available on the Fault Interrupt Status bit, FLTSTAT (PWMCONx<15>).

The FLTSTAT bit (PWMCONx<15>) displays the fault IRQ latch. If fault interrupts are not

enabled, the FLTSTAT bit (PWMCONx<15>) displays the status of the selected FLTx input in

positive logic format. When the fault input pins are not used in association with a PWM generator,

these pins can be used as general purpose I/O or interrupt input pins.

In addition to its operation as the PWM logic, the fault pin logic can also operate as an external

interrupt pin. If the faults are not allowed to affect the PWM generators in the FCLCONx register,

the fault pin can be used as a general purpose interrupt pin.

43.10.2.1 FAULT INPUT PIN MODES

The fault input pin consists of the following modes of operation:

• Latched mode: In Latched mode, the PWM outputs follow the states defined in the FLTDAT

bits in the IOCONx registers when the fault pin is asserted. The PWM outputs remain in this

state until the fault pin is deasserted and the corresponding interrupt flag is cleared in soft-

ware. When both these actions occur and the appropriate fault exit sequence (as described

in 43.10.4 “Fault Exit”) is followed the PWM outputs return to normal operation at the begin-

ning of next PWM cycle boundary. If the FLTSTAT bit (PWMCONx<15>) is cleared before the

Fault condition ends, the High-Speed PWM module waits until the fault pin is no longer

asserted. Software can clear the FLTSTAT bit (PWMCONx<15>) by writing ‘0’ to the FLTIEN

bit (PWMCONx<12>).

• Cycle-by-Cycle mode: In Cycle-by-Cycle mode, the PWM outputs remain in the deas-

serted PWM state as long as the fault input pin remains asserted. In Complementary PWM

Output mode, PWMxH is low (deasserted) and PWMxL is high (asserted). After the fault pin

is driven high, the PWM outputs return to normal operation at the beginning of the following

PWM cycle.

The operating mode for each fault input pin is selected using the FLTMOD<1:0>

bits (FCLCONx<1:0>).

43.10.3 Fault Entry

With respect to the device clock signals, the PWM pins always provide asynchronous response

to the fault input pins. Therefore, if FLTDAT bits are deasserted(set to ‘0’) the PWM generator

will immediately deassert the associated PWM outputs and if the specified FLTDAT bits are

asserted (set to ‘1’), the FLTDAT<1:0> bits (High/Low) (IOCONx<5:4>) are processed by the

dead time logic prior to being output as a PWM signal.

For more information on data sensitivity and behavior in response to the current-limit or Fault

events, refer to 43.12.4 “Fault/Current-Limit Override and Dead Time Logic”.

43.10.4 Fault Exit

After a Fault condition has ended, the PWM signals must be restored at a PWM cycle boundary

to ensure proper synchronization of PWM signal edges and manual signal overrides.

If Cycle-by-Cycle Fault mode is selected, the fault is automatically reset on every PWM cycle. No

additional coding is needed to exit the Fault condition.

For Latched Fault mode, the following sequence must be followed to exit the Fault condition:

1. Poll the PWM Fault source to determine if the fault signal has been deasserted.

2. Set the OVRDAT<1:0> (IOCONx<7:6>) bits to ‘0’.

3. Enable overrides for PWMxH and PWMxL by setting the OVRENH (IOCONx<9>) and

Note: In RPx, if x = 32, 33, 34 or 35, the comparator output is remapped to a virtual pin,

which is unavailable to the user.