Specifications

dsPIC33F/PIC24H Family Reference Manual

43.10 PWM FAULT PINS

The key functions of the PWM Fault input pins are as follows:

• For devices with re-mappable I/Os each PWM generator can select its fault input source

from up to eight Fault sources (the input to each of the fault sources can be assigned as

any of the re-mappable pins or the outputs of analog comparators using the virtual pins). To

configure the analog comparator as one of the Fault sources, refer to 43.10.1 “PWM Fault

Generated by the Analog Comparator”.

• For devices without re-mappable I/Os each PWM generator can select its fault input source

from up to 23 Fault pins and up to four analog comparator outputs.

• Each PWM generator has Fault Control Signal Source Select bits (FLTSRC<4:0>) in the

PWM Fault Current-Limit Control registers (FCLCONx<7:3>). These bits specify the source

for its fault input signal.

• Each PWM generator has the Fault Interrupt Enable bit, FLTIEN (PWMCONx<12>). This

bit enables the generation of fault IRQs.

• Each PWM generator has an associated Fault Polarity bit FLTPOL (FCLCONx<2>). This

bit selects the active state of the selected fault input.

• Upon occurrence of a Fault condition, the PWMxH and PWMxL outputs can be forced to

one of the following states:

- If Independent Fault Mode bit, IFLTMOD(FCLCONx<15>) is enabled, the

FLTDAT<1:0> bits (High/Low) (IOCONx<5:4>) provides data values to be assigned to

the PWMxH and PWMxL outputs. In this mode, the current limit source provides the

fault input for PWMxH pin and Fault source provides the fault input for PWMxL pin and

CLDAT<1:0> bits are ignored.

- In the Fault mode, the FLTDAT<1:0> bits (High/Low) (IOCONx<5:4>) provide the data

values to be assigned to the PWMxH and PWMxL outputs.

The following list describes major functions of the fault input pin:

• A fault can override the PWM outputs. The Fault Override Data bits, (FLTDAT<1:0>)

(IOCONx<5:4>) can have a value of either ‘0’ or ‘1’. If FLTDAT is set to ‘0’, it is processed

asynchronously to enable the immediate shutdown of the associated power transistors in

the application circuit. If FLTDAT is set to ‘1’, it is processed by the dead time logic and then

applied to the PWM outputs.

• The fault signals can generate interrupts. The FLTIEN bit (PWMCONx<12>) controls the

fault interrupt signal generation. The user-assigned application can specify interrupt signal

generation even if the Fault Mode bits, FLTMOD<1:0> (FCLCONx<1:0>), disable the fault

override function. This allows the fault input signal to be used as a general purpose exter-

nal IRQ signal.

• The fault input signal that can be used as a trigger signal to the ADC, which initiates an

ADC conversion process. The ADC trigger signals are always active regardless of the state

of the High-Speed PWM module, the FLTMOD<1:0> bits (FCLCONx<1:0>), or the

FLTIEN bit (PWMCONx<12>).

The FLTx pins are normally active-high. The FLTPOL bit (FCLCONx<2>), when set to ‘1’, inverts

the selected fault input signal; therefore, these pins are set as active-low.

The fault pins are also readable through the port I/O logic when the High-Speed PWM module is

enabled. This allows the user-assigned application to poll the state of the fault pins in software.