Specifications

dsPIC33F/PIC24H Family Reference Manual

43.8 PWM INTERRUPTS

The High-Speed PWM module can generate interrupts based on internal timing signals or

external signals through the current-limit and fault inputs. The primary time base module can

generate an IRQ when a specified event occurs. Each PWM generator module provides its own

IRQ signal to the interrupt controller. The interrupt for each PWM generator is a Boolean OR of

the trigger event IRQ, the current-limit input event, and the fault input event for that module.

Besides the individual PWM IRQs from each of the PWM generators, the interrupt controller

receives an IRQ signal from the primary time base on special events.

The three IRQs coming from each PWM generator are called Individual PWM interrupts. The IRQ

for each of the individual interrupts can come from the PWM individual trigger, PWM fault logic,

or PWM current-limit logic. Each PWM generator consists of the PWM interrupt flag in an IFSx

associated with the selected PWM generator is set.

If more than one IRQ source is enabled, the interrupt source is determined using the

user-assigned application by checking the Trigger Interrupt Status bit, TRGSTAT

(PWMCONx<13>), the Fault Interrupt Status bit, FLTSTAT (PWMCONx<15>), and the

Current-Limit Interrupt Status bit, CLSTAT (PWMCONx<14>).

43.8.1 PWM Time Base Interrupts

In each PWM generator, the High-Speed PWM module can generate interrupts based on the

master time base and/or the individual time base. The SEVTCMP register specifies timer based

interrupts for the primary time base, and the TRIGx registers specify timer based interrupts for

the individual time bases.

The primary time base special event interrupt is enabled through the SEIEN bit (PTCON<11>).

In each PWM generator, the individual time base interrupts generated by the trigger logic are

controlled by the TRGIEN bits (PWMCON<10>).

Note: When an appropriate match condition occurs, the Special Event Trigger signal and

the individual PWM trigger pulses to the ADC are always generated regardless of

the setting of their respective interrupt enable bits.