Specifications

Section 43. High-Speed PWM

High-Speed PWM

Figure 43-26: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 2, TRGSTRT = 2)

Figure 43-27: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 2, TRGSTRT = 3)

The trigger divider allows the user-assigned application to tailor the ADC sample rates to the

requirements of the control loop.

When the Dual Trigger Mode bit, DTM (TRGCONx<7>), is set to ‘1’, the ADC TRIGx output is a

Boolean OR of the ADC trigger pulses for the TRIGx and the STRIGx time base comparisons.

The DTM mode of operation allows the user-assigned application to take two ADC samples on

the same pin within a single PWM cycle.

If ADC triggers are generated at a rate faster than the rate that the ADC can process, the

operation can result in loss of some samples. However, the user-assigned application can

ensure that the time it provides is enough to complete two ADC operations within a single PWM

cycle.

The trigger pulse is generated regardless of the state of the Trigger Interrupt Enable bit, TRGIEN

(PWMCONx<10>). If the TRGIEN bit (PWMCONx<10>) is set to ‘1’, an interrupt request (IRQ)

is generated. The configuration of independent PWM ADC triggering is shown in Example 43-18.

PWMxH

TRIGx = 0

TRIGx = 8

TRIGx = 4808

TRIGx = 9616

PTPER = 9616

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