Specifications

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Section 43. High-Speed PWM

High-Speed PWM

Based on Equation 43-5, when the master, independent primary or independent secondary duty

cycle is used, the register value is loaded in the MDC, PDCx or SDCx register, respectively. The

PWM duty cycle selection is shown in Example 43-12. The PWM duty cycle initialization is shown

in Example 43-13.

Example 43-12: PWM Duty Cycle Selection

Example 43-13: PWM Duty Cycle Initialization

43.6.2.4 DUTY CYCLE RESOLUTION

When ACLK = 120 MHz, the PWM duty cycle and period resolution is 1.04 ns per LSb with the

PWM clock configured for the highest prescaler setting. The PWM duty cycle bit resolution can

be determined using Equation 43-6:

Equation 43-6: Bit Resolution Calculation

The duty cycle bit resolution versus PWM frequencies at highest PWM clock frequency is shown

in Table 43-1.

At the highest clock frequency, the clock period is 1.04 ns. The PWM resolution becomes coarser

by configuring other PWM clock prescaler settings.

Table 43-1: PWM Frequency and Duty Cycle Resolution

PWM Duty Cycle Resolution PWM Frequency

16 bits 14.6 kHz

15 bits 29.3 kHz

14 bits 58.6 kHz

13 bits 117.2 kHz

12 bits 234.4 kHz

11 bits 468.9 kHz

10 bits 937.9 kHz

9 bits 1.87 MHz

8 bits 3.75 MHz

/* Select either Master Duty cycle or Independent Duty cycle */

PWMCON1bits.MDCS = 0; /* PDC

X/SDCX provides duty cycle value */

PWMCON1bits.MDCS = 1; /* MDC provides duty cycle value */

/* Initialize PWM Duty cycle value */

PDC1 = 4794;/* Independent Primary Duty Cycle is 5 µs from Equation 43-5 */

SDC1 = 4794;/* Independent Secondary Duty Cycle is 5 µs from Equation 43-5 */

MDC = 4794; /* Master Duty Cycle is 5 µs from Equation 43-5 */

BitResolution log

ACLK 8× DesiredPWMPeriod×

PWMInputClockPrescalerDivider PCLKDIV()

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×=

Where,

DesiredPWMPeriod

DesiredPWMSwitchingFrequency

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