Specifications
© 2008-2012 Microchip Technology Inc. DS70323E-page 43-43
Section 43. High-Speed PWM
High-Speed PWM
43
43.5.7 Special Event Trigger
The High-Speed PWM module consists of a master Special Event Trigger that can be used as a
CPU interrupt source and for synchronization of analog-to-digital conversions with the PWM time
base. The analog-to-digital sampling time can be programmed to occur any time within the PWM
period. The Special Event Trigger allows the user-assigned application to minimize the delay
between the time the analog-to-digital conversion results are acquired and the time the duty cycle
value is updated. The Special Event Trigger is based on the master time base.
The master Special Event Trigger value is loaded into the PWM Special Event Compare
register (SEVTCMP/SSEVTCMP). In addition, the PWM Special Event Trigger Output
Postscaler Select bits (SEVTPS<3:0>) in the PWM Time Base Control register (PTCON<3:0>)
or the PWM Secondary Master Time Base Control register (STCON<3:0>), control the Special
Event Trigger operation. To generate a trigger to the ADC module, the value in the PWM Master
Time Base Counter (PMTMR/SMTMR) is compared to the value in the SEVTCMP/SSEVTCMP
register. The Special Event Trigger consists of a postscaler that allows 1:1 to 1:16 postscaler
ratio. The postscaler is configured by writing to the (SEVTPS<3:0>) control bits (PTCON<3:0>).
Special Event Trigger pulses are generated if the following conditions are satisfied:
• On a match condition regardless of the status of the Special Event Interrupt Enable bit,
SEIEN bit (PTCON<11>)
• If the compare value in the SEVTCMP/SSEVTCMP register is a value from zero to a
maximum value of the PTPER/STPER register
The Special Event Trigger output postscaler is cleared on these events:
• Any device Reset
• When PTEN = 0 (PTCON<15>)
The configuration of ADC special event trigger is shown in Example 43-7.
Example 43-7: ADC Special Event Trigger Configuration
In addition to generating ADC triggers, the Special Event Trigger can also be used to generate
the primary and secondary Special Event trigger interrupts, on a compare match event.
/* ADC Special Event Trigger configuration */
SEVTCMP = 1248; /* Special Event Trigger value set at ~25%
of period value (4999)*/
PTCONbits.SEVTPS = 0; /* Special Event Trigger output postscaler
set to 1:1 selection (trigger generated
every PWM cycle */
PTCONbits.SEIEN = 0; /* Special event interrupt is disabled */
while (PTCONbits.SESTAT == 0); /* Wait for special event status change */