Specifications

© 2008-2012 Microchip Technology Inc. DS70323E-page 43-29
Section 43. High-Speed PWM
High-Speed PWM
43
Register 43-25: LEBDLYx: Leading-Edge Blanking Delay Register
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
LEB<8:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
LEB<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0
bit 11-3 LEB<8:0>: Leading-Edge Blanking Delay bits for Current-Limit and Fault Inputs
Value in 8.32 ns increments.
bit 2-0 Unimplemented: Read as ‘0
Note: At the highest PWM resolution, the LEB<8:0> bits support the blanking (ignoring) of the current-limit and
Fault pins for a period of 0 ns to 4252 ns in 8.32 ns increments, following any specified rising and falling
edge of the PWMxH and PWMxL signals.