Specifications

Section 43. High-Speed PWM

High-Speed PWM

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHR PHF PLR PLF FLTLEBEN CLLEBEN LEB<6:5>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

LEB<4:0>

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PHR: PWMxH Rising Edge Trigger Enable bit

1 = Rising edge of PWMxH will trigger leading-edge blanking counter

0 = Leading-edge blanking ignores rising edge of PWMxH

bit 14 PHF: PWMxH Falling Edge Trigger Enable bit

1 = Falling edge of PWMxH will trigger leading-edge blanking counter

0 = Leading-edge blanking ignores falling edge of PWMxH

bit 13 PLR: PWMxL Rising Edge Trigger Enable bit

1 = Rising edge of PWMxL will trigger leading-edge blanking counter

0 = Leading-edge blanking ignores rising edge of PWMxL

bit 12 PLF: PWMxL Falling Edge Trigger Enable bit

1 = Falling edge of PWMxL will trigger leading-edge blanking counter

0 = Leading-edge blanking ignores falling edge of PWMxL

bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit

1 = Leading-edge blanking is applied to selected fault input

0 = Leading-edge blanking is not applied to selected fault input

bit 10 CLLEBEN: Current-limit Leading-Edge Blanking Enable bit

1 = Leading-edge blanking is applied to selected current-limit input

0 = Leading-edge blanking is not applied to selected current-limit input

bit 9-3 LEB<6:0>: Leading-Edge Blanking for Current-Limit and Fault Input bits

The Blanking can be incremented in 2

* 1/(Auxiliary Clock Frequency) ns steps, where ’n’ is the

PCLKDIV<2:0> bits (PTCON2<2:0>) setting.

bit 2-0 Unimplemented: Read as ‘0’

Note: At the highest PWM resolution, the LEB<6:0> bits support the blanking (ignoring) of the current-limit and

Fault pins for a period of 0 ns to 1057 ns in 8.32 ns increments, following any specified rising and falling

edge of the PWMxH and PWMxL signals.