Specifications

dsPIC33F/PIC24H Family Reference Manual

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDCx<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDCx<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PDCx<15:0>: PWM Generator x Duty Cycle Value bits

Note 1: In Independent Output mode, the PDCx register controls the PWMxH duty cycle only. In Complementary,

Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of PWMxH and PWMxL.

2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,

while the maximum pulse width generated corresponds to a value of Period + 0x0008.

3: PDCx < 0x0008 produces 0% duty cycle. PDCx > Period + 0x0008 produces 100% duty cycle.

4: As the Duty Cycle gets closer to 0% or 100% of the PWM Period (0 ns to 40 ns, depending on the mode

of operation), the PWM Duty Cycle resolution will increase from 1 LSb to 3 LSbs.