Specifications

dsPIC33F/PIC24H Family Reference Manual
DS70323E-page 43-12 © 2008-2012 Microchip Technology Inc.
Register 43-7: STPER: Secondary Master Time Base Period Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<15:8>
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
STPER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits
Note 1: The PWM time base has a minimum value of 0x0010, and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant 3 bits (LSbs) set to ‘0’. This
yields a period resolution of 8.32 ns (at fastest Auxiliary Clock rate) for these very short PWM period
pulses.
Register 43-8: SSEVTCMP: PWM Secondary Special Event Compare Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SSEVTCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
SSEVTCMP<4:0>
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 SSEVTCMP<12:0>: PWM Secondary Special Event Compare Count Value bits
bit 2-0 Unimplemented: Read as ‘0’
Note 1: 1 LSb = 1.04 ns. Therefore, minimum SSEVTCMP resolution is 8.32 ns at the fastest PWM Clock divider
setting (STCON2<2:0> = 0).
2: The Secondary Special Event Trigger is generated on a compare match with the PWM Secondary Master
Time Base Counter (SMTMR).
3: This register is used in conjunction with the STCON<3:0> bit field.