Specifications

dsPIC33F/PIC24H Family Reference Manual

Revision E (July 2012) (Continued)

• Sections:

- Updated “The SYNCO signal pulse 200 ns ensures that other devices reliably sense

the signals” to “The SYNCO signal pulse is 12 T

CY clocks wide (about 300 ns at

40 MIPS) to ensure other devices can sense the signal”, in 43.5.6 “Time Base

Synchronization”

- Replaced Least Significant Byte (LSB) with LSb in 43.6.2.4 “Duty Cycle Resolution”

- Updated the term ‘pin’ to ‘GPIO pin’ in the following sentence: When the port bit for the

pin is set, the fault input will be activated, in 43.10.6 “Fault Pin Software Control”

- Updated the following in 43.10.7 “PWM Current-Limit Pins”:

• Updated the first bullet

• Updated the term “fault input signal” to “current-limit signal” in the second bullet

• Updated the sub bullet “In Independent Fault mode of the IFLTMOD bit, the

CLDAT<1:0> bits are not used for override functions” to “If the Independent Fault

Enable bit, IFLTMOD (FCLCONx<15>) is set, the CLDAT<1:0> bits (IOCONx<3:2>)

are not used for override functions”

• Updated the sub bullet “In the Current-Limit Mode Enable bit (CLMOD), the

current-limit function is enabled. The CLDAT<1:0> bits (High/Low) supply the data

values to be assigned to the PWMxH and PWMxL outputs” to “If the IFLTMOD bit

(FCLCONx<15>) is clear, and the CLMOD bit (FCLCONx<8>) is set, enabling the

current-limit function, then the CLDAT<1:0> bits (High/Low) (IOCONx<3:2>) supply the

data values to be assigned to the PWMxH and PWMxL outputs when a current limit is

active”

• Tables:

- Updated bit 6 to bit 4 for the PWM Clock Prescaler 1:1 in the 16 ns column, in

Table 43-2

• Minor updates to text and formatting were incorporated throughout the document