Specifications

© 2008-2012 Microchip Technology Inc. DS70323E-page 43-115
Section 43. High-Speed PWM
High-Speed PWM
43
Revision E (July 2012)
This revision incorporates the following updates:
•Examples:
- Updated 8 MHz to 7.37 MHz, and updated 120 MHz to 117.9 MHz, in Example 43-2
• Equations:
- Added Equation title for Equation 43-1 through Equation 43-3
- Updated 1.04 ns to 1.06 ns in “The maximum PWM Duty Cycle resolution is 1.04 ns”,
in Equation 43-5
• Figures:
- Updated the label F
VCO
(1)
(120 MHz max) to FVCO
(1)
(80 MHz to 120 MHz max), in
Figure 43-3
- Updated Figure 43-8
- Updated the label “clk” to “CLK” in Figure 43-12 and Figure 43-13
- Updated the font of the decimal numbers to Computer text in the figure title, in
Figure 43-22, Figure 43-25 through Figure 43-27
- Updated PTMTMR to PMTMR in Figure 43-28
• Notes:
- Updated any references of LSB to LSb in Register 43-8, Register 43-10,
Register 43-12 and Register 43-13
- Updated Period - 0x0008 to Period + 0x0008 in Note 1and Note 2, in Register 43-10
- Updated Period - 0x0008 to Period + 0x0008 in Note 2 and Note 3, in Register 43-12
and Register 43-13
- Updated 1023 ns to 1058 ns in Note 1, in Register 43-23
- Updated the following in Register 43-24:
• Removed Note 1, and removed the Note 1 reference in register title
• Updated the note references for bit 5 and bit 4
- Updated 1023 ns to 4258 ns in the Note 1, in Register 43-25
- Added Note 2 in the note box below Equation 43-1, in 43.5.1 “PWM Clock Selection”
- Updated the following in 43.5.6 “Time Base Synchronization”:
• Replaced Note 1: The period of SYNCI pulse should be smaller than the PWM period
value to Note 1: The period of SYNCI pulse should be larger than the PWM period
value
• Added Note 5
- Updated SCDx to SDCx in the Note, in Figure 43-13
- Updated - 0x0008 to + 0x0008 in the Note 1 (above Equation 43-5), in
43.6.2.3 “Secondary Duty Cycle (SDCx)”
- Added a note in 43.6.8 “Dead Time Insertion in Center-Aligned Mode”
- Updated the note in 43.10.1 “PWM Fault Generated by the Analog Comparator”
- Added a note in 43.13 “Immediate Update of PWM Duty Cycle”
- Added a note in 43.15 “External Control of Individual Time Base(s) (Current Reset
Mode)”
•Registers:
- Updated PMTMR to SMTMR in Register 43-7
- Updated the bit 15-3 name in Register 43-8
- Updated any references of PWMLx and PWMHx to PWMxL and PWMxH in
Register 43-11
- Updated the bit value 0 description for bit 0, in Register 43-11
- Updated OVDDAT<1:0> bits to OVRDAT<1:0> bits for bit 0, in Register 43-19
- Updated 2
n
* 8.32 ns to 2
n
* [1/(Auxiliary Clock Frequency)] ns, in Register 43-23