Specifications

dsPIC33F/PIC24H Family Reference Manual
DS70323E-page 43-112 © 2008-2012 Microchip Technology Inc.
Revision C (March 2010) (Continued)
- Added a Note on power-saving modes, in 43.14.2 “High-Speed PWM Operation in
Idle Mode”
- Updated the Note in 43.16.5 “Current Reset PWM”
•Registers:
- Updated the register description for “PWMCAPx: Primary PWM Time Base Capture
Register”, in 43.3 “Control Registers”
- Corrected the term “PDCx” as “MDC/PDCx/SDCx” in the bit text ‘0’ description for
bit 0, in Register 43-11
- Corrected the term “Data” as “State” in bit 3-2, bit 5-4 and bit 7-6, in Register 43-19
- Rearranged Register 43-17: STRIGx: PWM Secondary Trigger Compare Value
Register after Register 43-20 as Register 43-21
- Corrected the bit text description for bit 9-3 as “The Blanking can be incremented
in 8.32 ns steps” in Register 43-23
• Sections:
- Added “Interleaved Power Factor Correction (IPFC)” in the common applications for
the High-Speed PWM, in 43.1 “Introduction”
- Updated the following changes in the list of major High-Speed PWM features,
in 43.2 “Features”
• Removed “PWM Capture feature”
• Updated “Dual trigger from PWM to Analog-to-Digital Converter (ADC) per PWM
period” as “Dual trigger to Analog-to-Digital Converter (ADC) per PWM period”
• Updated “Remappable PWMxH and PWMxL Pins” as “Remappable PWM4H and
PWM4L pins”
- Updated the following changes in 43.5.1 “PWM Clock Selection”:
• Added the term “Primary PLL Output (F
VCO)” in the first paragraph
• Corrected the term “PLLCLK” as “F
VCO” in the following description: The auxiliary
clock for the PWM module can be derived from the system clock while the device is
running in the primary PLL mode. Equation 43-3 gives the relationship between the
Primary PLL Clock (F
VCO) frequency and the Auxiliary Clock (ACLK) frequency.
- Added 43.5.4.1 “Advantages of Center-Aligned Mode in UPS Applications”.
- Updated the following changes in 43.5.6 “Time Base Synchronization”:
• Corrected the pulse width “130 ns” as “200 ns”
• Added the following description: The SYNCO signal pulse 200 ns ensures that other
devices reliably sense the signals
- Updated the event “When PTEN = 0” as “When PTCON<PTEN> = 0”,
in 43.5.7 “Special Event Trigger”
- Deleted the following description in 43.5.8 “Independent PWM Time Base”: The
PHASEx and SPHASEx registers provide the time period value for the PWMx
outputs (PWMxH and PWMxL) in Independent Time Base mode
- Updated the following changes in 43.6.3 “Dead Time Generation”:
• Added the following description: Dead time is not supported for Independent PWM
Output mode
• Removed “(gating)” in the description
- Added the following description in the “Negative Dead Time” sub-section,
in 43.6.4 “Dead Time Generators”: Negative dead time is specified only for
complementary PWM output signals
- Deleted the following description in 43.6.7 “Dead Time Resolution”: If devices do not
implement the High-Resolution PWM option and the PWM clock prescaler resolution
is 1.04 ns, 2.08 ns or 4.16 ns, the highest possible dead time resolution is 8.32 ns
- Updated “Dual Trigger Mode bit (DTM<7>) in the TRGCONx register” as “Dual Trigger
Mode bit (DTM) in the PWM Trigger Control register (TRGCONx<DTM> = 7)” in
43.7 “PWM Triggers”