Specifications

© 2008-2012 Microchip Technology Inc. DS70323E-page 43-111
Section 43. High-Speed PWM
High-Speed PWM
43
Revision C (March 2010)
• Equations:
- Updated the following equations: Equation 43-1, Equation 43-3 through Equation 43-7
- Added the following equations: Equation 43-2 and Equation 43-9
•Examples:
- Updated the following examples:
• Example 43-1, Example 43-4, Example 43-8, Example 43-11 and Example 43-23
• Updated the following changes in Example 43-2: Updated the example and
re-arranged the example to be placed after Example 43-1
• Updated the following changes in Example 43-12 and Example 43-13: Updated the
example and re-arranged the example from 43.6.2.4 “Duty Cycle Resolution”
to 43.6.2.3 “Secondary Duty Cycle (SDCx)”
- Added the following examples: Example 43-3, Example 43-5, Example 43-14,
Example 43-21, Example 43-22 and Example 43-29
• Figures:
- Updated the following figures: Figure 43-7, Figure 43-9, Figure 43-10, Figure 43-20
through Figure 43-27, Figure 43-33, Figure 43-36, Figure 43-39 through Figure 43-54
- Added the following figures: Figure 43-3, Figure 43-4, Figure 43-8, Figure 43-38,
Figure 43-49 and Figure 43-50
• Notes:
- Added a Note with information to customer for utilizing family reference manual
sections and data sheets as a joint reference (see note above 43.1 “Introduction”)
- Added Note 2 in Register 43-2 and Register 43-3
- Added a Note 1 in Register 43-4
- Added Note 5 in Register 43-11
- Updated the following changes in Register 43-14:
• Added a sub note in Note 1 and Note 2
• Deleted a sub note in Note 2
- Updated the following changes in
Register 43-15:
• Updated the second sub note in Note 1
• Updated the sub note in Note 2
- Updated the bit text description for bit 13-0, in Register 43-16 and Register 43-17
- Deleted the note reference for bit 7, and deleted the following note in Register 43-18:
The secondary PWM generator cannot generate PWM trigger interrupts
- Added Note 2 in Register 43-19
- Added a Note in Register 43-21
- Updated Note 1 in Register 43-22
- Added a Note 1 in Register 43-23
- Added Note 3 and Note 4 in Register 43-27
- Updated the following Note in 43.5.1 “PWM Clock Selection”: If the primary PLL is
used as a source for the auxiliary clock, then the primary PLL should be configured up
to a maximum operation of F
CY = 30 MHz or less, and FVCO must be in the range
of 112 MHz - 120 MHz
- Added Note 1 through Note 7 in 43.5.6 “Time Base Synchronization”
- Added a Note on duty cycle values in 43.6.7 “Dead Time Resolution”
- Added a Note on dynamic triggering in 43.7 “PWM Triggers”
- Deleted the following Note in Table 43-3: In the independent time base, the PWMxH
duty cycle is controlled by either MDC or PDCx, and the PWMxL duty cycle is
controlled by MDC or SDCx
- Deleted the following Note in Table 43-4: In the Independent output base, the PWMxH
duty cycle is controlled by either MDC or PDCx, and the PWMxL duty cycle is
controlled by MDC or SDCx