Specifications

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dsPIC33F/PIC24H Family Reference Manual

Table 43-9: High-Speed PWM Register Map for Devices without Remappable I/O

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

PTCON PTEN

— PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000

PTCON2

— — — — — — — — — — — — — PCLKDIV<2:0> 0000

PTPER PTPER<15:0> FFF8

SEVTCMP SEVTCMP<12:0>

— — — 0000

STCON

— — — SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC<2:0> SEVTPS<3:0> 0000

STCON2

— — — — — — — — — — — — — PCLKDIV<2:0> 0000

STPER STPER<15:0> FFF8

SSEVTCMP SSEVTCMP<12:0>

— — — 0000

CHOP CHPCLKEN

— — — — — CHOP<6:0> — — — 0000

MDC MDC<15:0> 0000

PWMCONx FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC<1:0> DTCP

— MTBS CAM XPRES IUE 0000

PDCx PDCx<15:0> 0000

SDCx SDCx<15:0> 0000

PHASEx PHASEx<15:0> 0000

SPHASEx SPHASEx<15:0> 0000

DTRx

— — DTRx<13:0> 0000

ALTDTRx

— — ALTDTRx<13:0> 0000

TRGCONx TRGDIV<3:0>

— — — —DTM—TRGSTRT<5:0>0000

IOCONx PENH PENL POLH POLL PMOD<1:0> OVRENH OVRENL OVRDAT<1:0> FLTDAT<1:0> CLDAT<1:0> SWAP OSYNC 0000

TRIGx TRGCMP<12:0>

— — — 0000

FCLCONx IFLTMOD CLSRC<4:0> CLPOL CLMOD FLTSRC<4:0> FLTPOL FLTMOD<1:0> 0000

STRIGx STRGCMP<12:0>

— — — 0000

LEBCONx PHR PHF PLR PLF FLTLEBEN CLLEBEN

— — — — BCH BCL BPHH BPHL BPLH BPLL 0000

LEBDLYx

— — — — LEB<8:0> — — — 0000

AUXCONx HRPDIS HRDDIS

— — BLANKSEL<3:0> — — CHOPSEL<3:0> CHOPHEN CHOPLEN 0000

PWMCAPx PWMCAPx<12:0>

— — — 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note: Not all bits in these registers are available on all devices. Refer to the “High-Speed PWM” chapter in the specific device data sheet for more information on available registers.