Section 43. High-Speed PWM HIGHLIGHTS This section of the manual contains the following major topics: © 2008-2012 Microchip Technology Inc. DS70323E-page 43-1 43 High-Speed PWM 43.1 Introduction .................................................................................................................. 43-2 43.2 Features....................................................................................................................... 43-2 43.3 Control Registers ................................
dsPIC33F/PIC24H Family Reference Manual Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on the device variant, this manual section may not apply to all dsPIC33F/PIC24H devices. Please consult the note at the beginning of the “High-Speed PWM” chapter in the current device data sheet to check whether this document supports the device you are using.
Section 43. High-Speed PWM 43.3 CONTROL REGISTERS This section outlines the specific functions of each register that controls the operation of High-Speed PWM module. © 2008-2012 Microchip Technology Inc.
dsPIC33F/PIC24H Family Reference Manual • PHASEx: PWM Primary Phase Shift Register - Provides the phase shift value for the PWMxH and/or PWMxL outputs, if master time base is selected - Provides the independent time base period for the PWMxH and/or PWMxL outputs, if independent time base is selected • DTRx: PWM Dead Time Register - Provides the dead time value for the PWMxH output, if positive dead time is selected - Provides the dead time value for the PWMxL output, if negative dead time is selected • ALTD
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-1: PTCON: PWM Time Base Control Register R/W-0 PTEN(3) bit 15 U-0 — R/W-0 SYNCEN(1,2) bit 7 R/W-0 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-4 bit 3-0 Note 1: 2: 3: HS/HC-0 SESTAT R/W-0 R/W-0 SYNCSRC<2:0>(1,2) R/W-0 SEIEN R/W-0 EIPU(1) R/W-0 R/W-0 SYNCPOL(1,2) SYNCOEN(1,2) bit 8 R/W-0 R/W-0 R/W-0 SEVTPS<3:0>(1) R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 PTSIDL HC = Cleared in Hardware HS =
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-3: PTPER: Master Time Base Period Register R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PTPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PTPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PTPER<15:0>: Master Time Base (PMTMR) Period Value bits Note 1: The PWM time base
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-5: STCON: PWM Secondary Master Time Base Control Register U-0 U-0 — — U-0 HS/HC-0 — SESTAT R/W-0 SEIEN R/W-0 (1) EIPU R/W-0 SYNCPOL R/W-0 (1,2) SYNCOEN bit 15 bit 8 R/W-0 R/W-0 (1,2) R/W-0 SYNCSRC<2:0> SYNCEN R/W-0 R/W-0 R/W-0 (1) R/W-0 SEVTPS<3:0> bit 7 bit 0 Legend: HC = Cleared in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-7: STPER: Secondary Master Time Base Period Register R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 STPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 STPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits Note
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-11: PWMCONx: PWM Control Register HS/HC-0 HS/HC-0 FLTSTAT(1) CLSTAT (1) HS/HC-0 TRGSTAT R/W-0 R/W-0 FLTIEN CLIEN R/W-0 TRGIEN R/W-0 (3) ITB R/W-0 MDCS(3) bit 15 bit 8 R/W-0 R/W-0 DTC<1:0> (3) R/W-0 (3,6) DTCP U-0 R/W-0 — MTBS R/W-0 (2,3,5) CAM R/W-0 R/W-0 (4) XPRES bit 7 IUE bit 0 Legend: HC = Cleared in Hardware HS = Set in Hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at PO
Section 43. High-Speed PWM Register 43-11: PWMCONx: PWM Control Register (Continued) DTC<1:0>: Dead Time Control bits(3) 11 = Dead time Compensation mode 10 = Dead time function is disabled 01 = Negative dead time actively applied for all output modes 00 = Positive dead time actively applied for all output modes bit 5 DTCP: Dead-Time Compensation Polarity bit(3,6) When set to ‘1’: If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened. If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.
dsPIC33F/PIC24H Family Reference Manual Register 43-12: PDCx: PWM Generator Duty Cycle Register R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDCx<15:0>: PWM Generator x Duty Cycle Value bits Note 1: In Independent Output mode
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-14: PHASEx: PWM Primary Phase Shift Register R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PHASEx<15:0>: PWM Phase Shift Value or Independent Time Base Period bits for the
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-16: DTRx: PWM Dead Time Register U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-bit Dead Time Value bits for P
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-19: IOCONx: PWM I/O Control Register R/W-0 R/W-0 PENH PENL R/W-0 POLH R/W-0 POLL R/W-0 R/W-0 PMOD<1:0>(1) R/W-0 R/W-0 OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 OVRDAT<1:0>(2) R/W-0 R/W-0 FLTDAT<1:0>(2) R/W-0 R/W-0 CLDAT<1:0>(2) R/W-0 R/W-0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PEN
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-20: TRIGx: PWM Primary Trigger Compare Value Register R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<4:0> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 TRGCMP<12:0>: Trigger Control Value bits When the primary PWM funct
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-22: FCLCONx: PWM Fault Current-Limit Control Register (Continued) CLPOL: Current-limit Polarity bit for PWM Generator #(1) 1 = The selected current-limit source is active-low 0 = The selected current-limit source is active-high CLMOD: Current-limit Mode Enable bit for PWM Generator # 1 = Current-limit mode is enabled 0 = Current-limit mode is disabled FLTSRC<4:0>: Fault Control Signal Source Select bits for PWM Generator #(3,4) For devices with remappable
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-24: LEBCONx: Leading-Edge Blanking Control Register (Version 2) R/W-0 PHR bit 15 R/W-0 PHF R/W-0 PLR R/W-0 PLF R/W-0 FLTLEBEN R/W-0 CLLEBEN U-0 — bit 8 U-0 — U-0 — R/W-0 BCH(1) R/W-0 BCL R/W-0 BPHH R/W-0 BPHL R/W-0 BPLH bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 BPLL bit 0 U = Unimp
Section 43.
dsPIC33F/PIC24H Family Reference Manual Register 43-26: AUXCONx: PWM Auxiliary Control Register R/W-0 R/W-0 U-0 U-0 HRPDIS HRDDIS — — R/W-0 R/W-0 R/W-0 R/W-0 BLANKSEL<3:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 CHOPSEL<3:0> R/W-0 R/W-0 CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HRPDIS: High-Resolution PWM Period Disabl
Section 43.
dsPIC33F/PIC24H Family Reference Manual 43.4 ARCHITECTURE OVERVIEW Figure 43-1 illustrates an architectural overview of the High-Speed PWM module and its interconnection with the CPU and other peripherals.
Section 43. High-Speed PWM The High-Speed PWM module contains upto nine PWM generators. Each PWM generator provides two PWM outputs: PWMxH and PWMxL. A master time base generator provides a synchronous signal as a common time base to synchronize the various PWM outputs. Each generator can operate independently or in synchronization with the master time base. The individual PWM outputs are available on the output pins of the device.
dsPIC33F/PIC24H Family Reference Manual Figure 43-2: High-Speed PWM Module Register Interconnection Diagram PTCON, PTCON2 SYNCI1 Module Control and Timing Special Event Postscaler Comparator Comparator SYNCI4 SYNCO1 Special Event Compare Trigger SEVTCMP PTPER SYNCI3 SYNCI2 Special Event Trigger Primary Master Time Base Counter Clock Prescaler PMTMR Primary Master Time Base SYNCI1 STPER SSEVTCMP Comparator Comparator Master Duty Cycle SYNCO2 Secondary Special Event Postscaler Seconda
Section 43. High-Speed PWM 43.5 MODULE DESCRIPTION 43.5.1 PWM Clock Selection The auxiliary clock generator must be used to generate the clock for the PWM module independent of the system clock. The Primary Oscillator Clock (POSCCLK), Primary Phase-Locked Loop (PLL) Output (FVCO), and Internal FRC Clock (FRCCLK) can be used with an auxiliary PLL to obtain the Auxiliary Clock (ACLK). The auxiliary PLL consists of a fixed 16x multiplication factor.
dsPIC33F/PIC24H Family Reference Manual For devices with remappable I/O, refer to Section 42. “Oscillator (Part IV)” (DS70307), for more information on configuring the clock generator. For devices without remappable I/O, refer to Section 48. “Oscillator (Part V)” (DS70596). Equation 43-1: ACLK Frequency Calculation × M1 ACLK = REFCLK -------------------------------------N Where, REFCLK = Internal FRC Clock frequency (7.
Section 43. High-Speed PWM The ACLK for the PWM module can be derived from the system clock while the device is running in the primary PLL mode. Equation 43-3 provides the relationship between the FVCO frequency and ACLK frequency. The block diagram for FVCO as the clock source for ACLK is illustrated in Figure 43-4. The formula to calculate Fvco is shown in Equation 43-2. The example for using FVCO as the auxiliary clock source is shown in Example 43-3.
dsPIC33F/PIC24H Family Reference Manual Example 43-3: Using FVCO as the Auxiliary Clock Source /* /* /* /* /* /* /* Assume Primary Oscillator is 8 MHz and FCY = 30 MHz. */ Therefore, FOSC = 60 MHz */ Setup for the Auxiliary clock to use Fvco as the source */ Fosc = Primary Oscillator * (PLLDIV / PLLPOST * PLLPRE) */ Fvco = Fosc * N2 */ Fosc = 60 MHz; N2 = 2; Fvco = 120 MHz; M = 30 */ Input to the Vco = 4 MHz; N1 = 2; Fin = 8 MHz */ ACLKCONbits.
Section 43. High-Speed PWM 43.5.4 Center-Aligned PWM The center-aligned PWM waveforms as illustrated in Figure 43-6, align the PWM signals to a reference point such that half of the PWM signal occurs before the reference point and the remaining half of the signal occurs after the reference point. Center-aligned mode is enabled when the Center-Aligned Mode Enable bit (CAM) in the PWM Control register (PWMCONx<2>) is set.
dsPIC33F/PIC24H Family Reference Manual 43.5.4.1 ADVANTAGES OF CENTER-ALIGNED MODE IN UPS APPLICATIONS The current ripple frequency and noise frequency are double the switch frequency. A lower magnitude of current ripple is achieved as the switch frequency of the current ripple is doubled. Lower current ripple contributes to relaxed requirements for the DC input capacitor and output filter inductor and capacitor. Lower current ripple contributes to lower output current harmonics.
Section 43. High-Speed PWM 43.5.5 Master Time Base/Synchronous Time Base The PWM functionality in the master time base is illustrated in Figure 43-9.
dsPIC33F/PIC24H Family Reference Manual 43.5.6 Time Base Synchronization The master time base can be synchronized with the external synchronization signal through the master time base synchronization signal (SYNCI1/SYNCI2/SYNCI3/SYNCI4). The synchronization source (SYNCI1, SYNCI2, SYNCI3 and SYNCI4), can be selected using the Synchronous Source Selection bits (SYNCSRC<1:0>) in the PWM Time Base Control register (PTCON<5:4>).
Section 43. High-Speed PWM 43.5.7 Special Event Trigger The High-Speed PWM module consists of a master Special Event Trigger that can be used as a CPU interrupt source and for synchronization of analog-to-digital conversions with the PWM time base. The analog-to-digital sampling time can be programmed to occur any time within the PWM period.
dsPIC33F/PIC24H Family Reference Manual 43.5.8 Independent PWM Time Base The PWM functionality in the independent time base is illustrated in Figure 43-10.
Section 43. High-Speed PWM 43.6 PWM GENERATOR This section describes the functionality of the PWM generator. 43.6.1 PWM Period The PWM period value defines the switching frequency of the PWM pulses. The PWM period value can be controlled either by the PTPER/STPER register, or by the Independent Time Period PHASEx and SPHASEx registers for the respective primary and secondary PWM outputs.
dsPIC33F/PIC24H Family Reference Manual Based on Equation 43-4, while operating in the PTPER register or the PHASEx and SPHASEx registers, the register value to be loaded is shown in Example 43-8. Example 43-8: PWM Time Period Calculation ACLK = 7.49 MHz * 16 = 119.84 MHz 1 Where, REFCLK = 7.49 MHz M1 = 16 N=1 PTPER, STPER, PHASEx, SPHASEx = 119.
Section 43. High-Speed PWM 43.6.2 PWM Duty Cycle Control The duty cycle determines the period of time that the PWM output must remain in the active state. Each duty cycle register allows a 16-bit duty cycle value that is to be specified. The duty cycle values can be updated any time by setting the Immediate Update Enable bit, IUE (PWMCONx<0>). If the IUE bit (PWMCONx<0>) is ‘0’, the active Duty Cycle register (PDCx, SDCx or MDC) updates at the start of the next PWM cycle.
dsPIC33F/PIC24H Family Reference Manual Figure 43-13: Secondary Duty Cycle Comparison 15 0 CLK STMRx Compare Logic 0 PWMxL signal <= MDCS select MUX 1 15 0 SDCx Register 15 0 MDC Register Note: In Independent Output mode, SDCx affects PWMxL only, SDCx is ignored in all other PWM output modes. The Duty Cycle can be determined using Equation 43-5.
Section 43. High-Speed PWM Based on Equation 43-5, when the master, independent primary or independent secondary duty cycle is used, the register value is loaded in the MDC, PDCx or SDCx register, respectively. The PWM duty cycle selection is shown in Example 43-12. The PWM duty cycle initialization is shown in Example 43-13. Example 43-12: PWM Duty Cycle Selection /* Select either Master Duty cycle or Independent Duty cycle */ PWMCON1bits.MDCS = 0; /* PDCX/SDCX provides duty cycle value */ PWMCON1bits.
dsPIC33F/PIC24H Family Reference Manual 43.6.3 Dead Time Generation Dead time refers to a programmable period of time (specified by the Dead Time register (DTRx) or the Alternate Dead Time registers (ALTDTRx)), which prevents a PWM output from being asserted until its complementary PWM signal has been deasserted for the specified time. The High-Speed PWM module consists of four dead time control units. Each dead time control unit has its own dead time value.
Section 43. High-Speed PWM 43.6.4 Dead Time Generators Each complementary output pair for the High-Speed PWM module has a 12-bit down counter to produce the dead time insertion. Each dead time unit has a rising and falling edge detector connected to the duty cycle comparison output. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the associated dead time timer generates the specific delay period.
dsPIC33F/PIC24H Family Reference Manual 43.6.5 Dead Time Ranges The dead time duration provided by each dead time unit is set by specifying an unsigned value in the DTRx and ALTDTRx registers. At maximum operating clock frequency with a 1.04 ns duty cycle resolution, the dead time resolution is 1.04 ns. At the highest PWM resolution, the maximum dead time value is 17.03 µs. 43.6.6 Dead Time Distortion For duty cycle values near 0% or 100%, the PWM signal becomes nonlinear if dead time is active.
Section 43. High-Speed PWM 43.6.8 Dead Time Insertion in Center-Aligned Mode While using Center-Aligned mode and complementary PWM, only the ALTDTRx register must be used for dead time insertion. The dead time is inserted in the PWM waveform is illustrated in Figure 43-15. Note: With IUE = 1, all the three cases as described in 43.13 “Immediate Update of PWM Duty Cycle” hold good in Center-aligned mode.
dsPIC33F/PIC24H Family Reference Manual Figure 43-16: Phase Shifting (Complementary Mode) PHASEx PWMxH without Phase Shift PWMxH with Phase Shift PWMxL without Phase Shift PWMxL with Phase Shift Note: In Complementary, Push-Pull and Redundant PWM Output modes, PHASEx controls the phase shift for PWMxH and PWMxL outputs.
Section 43. High-Speed PWM Figure 43-18: Phase Shift Waveforms PMTMR rollover on PTPER match PTPER =100 Master Time Base (PMTMR) Period Match Next Phase Requested PHASEx Next Phase 25 75 50 50 75 25 PHASEx 43 PTMRx High-Speed PWM SPHASEx PDCx Load PHASEx on MTB rollover PWMxH STMRx SDCx PWMxL Note: Operation of High-Speed PWM module with independent time base is controlled by the master time base. © 2008-2012 Microchip Technology Inc.
dsPIC33F/PIC24H Family Reference Manual Example 43-17: PWM Phase Shift Initialization /* Initialize phase shift value for the PWM output */ /* Phase shifts are initialized when operating in Master Time Base */ PHASEx = 100; /* Primary phase shift value of 104 ns */ SPHASEx = 100; /* Secondary phase shift value of 104 ns */ The bit resolution of PWM duty cycle, phase and dead time with respect to different input clock prescaler selections are shown in Table 43-2.
Section 43. High-Speed PWM 43.7 PWM TRIGGERS For the ADC module, the TRIGx and STRIGx registers specify the triggering point for the PWMxH and PWMxL outputs, respectively. An ADC trigger signal is generated when the independent time base counter (PTMRx or STMRx) register value matches with the specified TRIGx or STRIGx register value. The Output Divider bits (TRGDIV<3:0>) in the PWM Trigger Control register (TRGCONx<15:12) act as a postscaler for the TRIGx register to generate ADC triggers.
dsPIC33F/PIC24H Family Reference Manual Figure 43-20: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 0, TRGSTRT = 0) 1 2 3 4 5 6 7 PWMxH TRIGx = 0 TRIGx = 8 TRIGx = 4808 TRIGx = 9616 PTPER = 9616 Figure 43-21: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 0, TRGSTRT = 1) PWMxH 1 2 3 4 5 6 7 TRIGx = 0 TRIGx = 8 TRIGx = 4808 TRIGx = 9616 PTPER = 9616 DS70323E-page 43-58 © 2008-2012 Microchip Technology Inc.
Section 43. High-Speed PWM Figure 43-22: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 0, TRGSTRT = 2) PWMxH 1 2 3 4 5 TRIGx = 0 TRIGx = 8 TRIGx = 4808 TRIGx = 9616 PTPER = 9616 Figure 43-23: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 1, TRGSTRT = 0) 43 1 2 3 4 5 6 TRIGx = 0 TRIGx = 8 TRIGx = 4808 TRIGx = 9616 PTPER = 9616 © 2008-2012 Microchip Technology Inc.
dsPIC33F/PIC24H Family Reference Manual Figure 43-24: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 1, TRGSTRT = 1) PWMxH 1 2 3 4 5 6 7 TRIGx = 0 TRIGx = 8 TRIGx = 4808 TRIGx = 9616 PTPER = 9616 Figure 43-25: PWM Trigger Signal in Relation to the PWM Output (TRGDIV = 2, TRGSTRT = 0) PWMxH 1 2 3 4 5 6 7 TRIGx = 0 TRIGx = 8 TRIGx = 4808 TRIGx = 9616 PTPER = 9616 DS70323E-page 43-60 © 2008-2012 Microchip Technology Inc.
Section 43.
dsPIC33F/PIC24H Family Reference Manual Example 43-18: Independent PWM ADC Triggering /* Independent PWM ADC triggering */ TRIG1 = 1248; /* Point at which the ADC module is to be triggered by primary PWM */ STRIG1 = 2496; /* Point at which the ADC module is to be triggered by secondary PWM */ TRGCON1bits.TRGDIV = 0; /* Trigger output divider set to trigger ADC on every trigger match event */ TRGCON1bits.DTM = 1; /* Primary and Secondary triggers combined to create ADC trigger */ TRGCON1bits.
Section 43.
dsPIC33F/PIC24H Family Reference Manual 43.8 PWM INTERRUPTS The High-Speed PWM module can generate interrupts based on internal timing signals or external signals through the current-limit and fault inputs. The primary time base module can generate an IRQ when a specified event occurs. Each PWM generator module provides its own IRQ signal to the interrupt controller.
Section 43. High-Speed PWM 43.9 PWM OPERATING MODES This section describes the following operation modes, which are supported by the High-Speed PWM module: • • • • Push-Pull PWM Output Mode Complementary PWM Output Mode Redundant PWM Output Mode True Independent PWM Output Mode These operating modes can be selected using the PWM # I/O Pin Mode bits (PMOD<1:0>) in the PWM I/O Control register (IOCONx<11:10>). 43.9.
dsPIC33F/PIC24H Family Reference Manual 43.9.3 Redundant PWM Output Mode In Redundant PWM Output mode, the High-Speed PWM module has the ability to provide two copies of a single-ended PWM output signal per PWM pin pair (PWMxH, PWMxL). This mode uses the PDCx register to specify the duty cycle. In this output mode, the two PWM output pins provide the same PWM signal unless the user-assigned application specifies an override value. Redundant PWM Output mode is illustrated in Figure 43-31.
Section 43. High-Speed PWM 43.9.4 True Independent PWM Output Mode In True Independent PWM Output mode (PMOD = 11), the PWM outputs (PWMxH and PWMxL) can have different duty cycles. The PDCx register specifies the duty cycle for the PWMxH output, whereas the SDCx register specifies the duty cycle for the PWMxL output. In addition, the PWMxH and PWMxL outputs can either have different periods or they can be phase-shifted relative to each other.
dsPIC33F/PIC24H Family Reference Manual Example 43-19: PWM Output Pin Mode Selection /* Select PWM I/O pin Mode – Choose one of the following output modes */ IOCON1bits.PMOD = 0; /* For Complementary Output mode */ IOCON1bits.PMOD = 1; /* For Redundant Output mode */ IOCON1bits.PMOD = 2; /* For Push-Pull Output mode */ IOCON1bits.PMOD = 3; /* For True Independent Output mode */ Table 43-4 provides the PWM register functionality for the Independent Output mode.
Section 43.
dsPIC33F/PIC24H Family Reference Manual 43.10 PWM FAULT PINS The key functions of the PWM Fault input pins are as follows: • For devices with re-mappable I/Os each PWM generator can select its fault input source from up to eight Fault sources (the input to each of the fault sources can be assigned as any of the re-mappable pins or the outputs of analog comparators using the virtual pins). To configure the analog comparator as one of the Fault sources, refer to 43.10.
Section 43. High-Speed PWM Figure 43-33: PWM Fault Control Module Block Diagram for Devices with Remappable I/O PWMxH, PWMxL Signals 2 0 PWM Generator # 2 PWMxH, PWMxL FLTDAT<1:0> 2 1 Latch FLTSTAT PMTMR/SMTMR Clear 00000 FLT2 00001 FLT3 00010 FLT4 00011 FLT5 00100 FLT6 00101 FLT7 00110 FLT8 00111 Fault Mode Selection Logic 43 High-Speed PWM FLT1 FLTMOD<1:0> FLTSRC<4:0> © 2008-2012 Microchip Technology Inc.
dsPIC33F/PIC24H Family Reference Manual Figure 43-34: PWM Fault Control Module Block Diagram for Devices without Remappable I/O PWMxH, PWMxL Signals PWM Generator # CMP1x Analog Comparator 2 CMP2x Analog Comparator 3 CMP3x Analog Comparator 4 CMP4x 0 2 PWMxH, PWMxL FLTDAT<1:0> Analog Comparator Module Analog Comparator 1 2 2 1 00000 Latch 00001 FLTSTAT 00010 PMTMR/SMTMR 00011 Clear FLT1 01000 FLT2 01001 FLT3 01010 FLT4 01011 FLT5 01100 FLT6 01101 FLT7 01110 FLT8 01111 FLT23
Section 43. High-Speed PWM 43.10.1 PWM Fault Generated by the Analog Comparator Note: This section only applies to devices with remappable I/O. Refer to the Controller Family tables in the specific device data sheet for the list of available peripherals. For devices without remmappable I/O the analog comparators can be directly assigned as fault source by configuring the FLTSRC<4:0> (FCLCONx<7:3>) bits as shown in Figure 43-34.
dsPIC33F/PIC24H Family Reference Manual Note: In RPx, if x = 32, 33, 34 or 35, the comparator output is remapped to a virtual pin, which is unavailable to the user. 43.10.2 Fault Interrupts The FLTIENx bits (PWMCONx<12>) determine whether an interrupt will be generated when the FLTx input is asserted high. The FLTDAT<1:0> bits (High/Low) (IOCONx<5:4>) supply the data values to be assigned to the PWMxH and PWMxL pins in case of a fault.
Section 43. High-Speed PWM OVRENL(IOCONx<8>) to high. Disable the PWM fault by setting FLTMOD<1:0> bits (FCLCONx<1:0>) = ‘0b11. Provide a delay of at least 1 PWM cycle. Enable the PWM fault by setting FLTMOD<1:0> bits (FCLCONx<1:0>) =‘0b00. If PWM Fault interrupt is enabled then perform the following sub-steps and then proceed to step 8. If not then skip this step and proceed to step 8. - a) Complete the PWM fault Interrupt Service Routine.
dsPIC33F/PIC24H Family Reference Manual 43.10.7 PWM Current-Limit Pins The key functions of the PWM current-limit pins are as follows: • For devices with re-mappable I/Os each PWM generator can select its current-limit input source from up to eight Fault sources (the input to each of the fault sources can be assigned as any of the re-mappable pins or the outputs of analog comparators using the virtual pins). To configure the analog comparator as one of the current-limit sources, refer to 43.10.
Section 43. High-Speed PWM 43.10.7.1 CONFIGURATION OF CURRENT RESET MODE A current-limit signal resets the time base for the affected PWM generator with the following configuration: - The CLMOD bit for the PWM generator is ‘0’. - The External PWM Reset Control bit, XPRES (PWMCONx<1>) is ‘1’. - The PWM generator is in Independent Time Base mode (ITB = 1). The configuration of Current Reset mode is shown in Example 43-21. For more information, refer to 43.16.5 “Current Reset PWM”.
dsPIC33F/PIC24H Family Reference Manual Figure 43-37: PWM Current-Limit Control Circuit Logic Diagram for Devices without Remappable I/O 2 PWMxH, PWMxL Signals 0 PWM Generator # 2 PWMxH, PWMxL EN CLDAT<1:0> 2 1 XPRES CMP1x Analog Comparator Module Analog Comparator 1 CMP2x CMP3x CMP4x Analog Comparator 2 Analog Comparator 3 Analog Comparator 4 PMTMR/SMTMR 00000 Cycle-by-Cycle Mode 00001 00010 00011 FLT1 01000 FLT2 01001 FLT3 01010 FLT4 01011 FLT5 01100 FLT6 01101 FLT7 01110 FL
Section 43.
dsPIC33F/PIC24H Family Reference Manual The analog comparator provides high-speed operation with a typical delay of 20 ns. The positive input of the comparator is connected to an analog multiplexer (INSEL<1:0>) in the CMPCONx register. The positive input of the comparator measures the current signal (voltage signal). The negative input of the comparator is always connected to the DAC circuit. For more information, refer to Figure 45-1 in Section 45. “High-Speed Analog Comparator” (DS70296).
Section 43. High-Speed PWM 43.10.10 PWM Fault and Current-Limit Trigger Outputs to ADC The CLSRC<4:0> bits (FCLCONx<14:10>) and FLTSRC<4:0> bits (FCLCONx<7:3>) and control the fault selection to each PWM generator module. The control multiplexers select the desired fault and current-limit signals for their respective modules. The selected fault and current-limit signals which are also available to the ADC module as trigger signals, initiate ADC sampling and conversion operations.
dsPIC33F/PIC24H Family Reference Manual 43.11 SPECIAL FEATURES The following special features are available in the High-Speed PWM module: • • • • • Leading-Edge Blanking (LEB) Individual time base capture PWM pin swapping PWM output pin control and override PWM immediate update 43.11.
Section 43. High-Speed PWM Figure 43-39: Leading-Edge Blanking Switching Noise PWM Output High Power Signal Blanking Signal Power signal as seen by fault circuitry Fault and current-limit circuitry ignores the switching noise Blanking time is determined by the LEB<9:3> bits in the LEBCONx registers 43.11.2 Individual Time Base Capture The Capture register is used in current-limit PWM control applications that use the analog comparators or external circuitry to terminate the PWM duty cycle or period.
dsPIC33F/PIC24H Family Reference Manual Figure 43-40: Dead-Time Compensation Normal PWM Stretched PWM through DTR Shortened PWM through DTR DTCMPx selected PWMxH Create PWMxL PWMxH with ALDTR Dead Time PWMxL with ALDTR Dead Time Note: Dead-time compensation only applies to Complementary PWM Output mode. Specifying dead-time compensation in any other PWM Output mode will yield unpredictable results. 43.11.
Section 43. High-Speed PWM Figure 43-41: High-Frequency PWM Chopping 50 μsec Unchopped PWM 1 μsec Chopping Signal Chopped PWM Note: Not drawn to scale. The chopping function performs a logical AND operation of the PWM outputs. Because of the finite period of the chopping clock, the resultant PWM duty cycle resolution is limited to one half of the chop clock period.
dsPIC33F/PIC24H Family Reference Manual 43.11.5 PWM Pin Swapping The SWAP PWMxH and PWMxL Pins bit, SWAP (IOCONx<1>), if set to ‘1’, enables the user-assigned application to connect the PWMxH signal to the PWMxL pin and the PWMxL signal to the PWMxH pin. If the SWAP bit (IOCONx<1>) is set to ‘0’, the PWM signals are connected to their respective pins. To perform the swapping function on the PWM cycle boundaries, the Output Override Synchronization bit, OSYNC (IOCONx<0>), must be set.
Section 43. High-Speed PWM 43.11.5.2 EXAMPLE 2: PIN SWAPPING WITH MOTOR CONTROL The Motor Control example describes static swapping. Consider a generic motor control system, that is capable of driving two different types of motors, such as DC motors and three-phase AC induction motors. Brushed DC motors typically use a full-bridge transistor configuration, as illustrated in Figure 43-44.
dsPIC33F/PIC24H Family Reference Manual 43.12 PWM OUTPUT PIN CONTROL If the High-Speed PWM module is enabled, the priority of PWMxH/PWMxL pin ownership from lowest to highest priority is as follows: • • • • • • PWM generator (lowest priority) Swap function PWM output override logic Current-limit override logic Fault override logic PENX (GPIO/PWM) ownership (highest priority) If the High-Speed PWM module is disabled, the GPIO module controls the PWMx pins.
Section 43. High-Speed PWM Example 43-28: PWM Output Override Control /* Define override state of the PWM outputs. PWMxH and PWMxL outputs will be at logic level ‘0’when overridden. */ IOCON1bits.OVRDAT = 0; /* Override PWMxH and PWMxL outputs */ IOCON1bits.OVRENH = 1; __builtin_nop(); IOCON1bits.OVRENL = 1; . . . /* Clear overrides of PWMxH and PWMxL outputs */ IOCON1bits.OVRENH = 0; __builtin_nop(); IOCON1bits.OVRENL = 0; 43.12.
dsPIC33F/PIC24H Family Reference Manual 43.12.5 Asserting Outputs through Current-Limit In response to a Current-Limit event, the CLDAT bits (IOCONx<3:2>) can be used to assert the PWMxH and PWMxL outputs. Such behavior can be used as a current force feature in response to an external current or voltage measurement that indicates a sudden sharp increase in the load on the power-converter output.
Section 43. High-Speed PWM 43.13 IMMEDIATE UPDATE OF PWM DUTY CYCLE The high performance PWM control-loop application requires a maximum duty cycle update rate. Setting the IUE bit (PWMCONx<0>) enables this feature. In a closed-loop control application, any delay between the sensing of a system state and the subsequent output of PWM control signals that drive the application reduces the loop stability.
dsPIC33F/PIC24H Family Reference Manual 43.14 POWER-SAVING MODES This section discusses the operation of the High-Speed PWM module in Sleep mode and Idle mode. 43.14.1 High-Speed PWM Operation in Sleep Mode When the device enters Sleep mode, the system clock is disabled. Since the clock for the PWM time base is derived from the system clock source (TCY), that clock is also disabled and all enabled PWM output pins that are in effect prior to entering Sleep mode are frozen in the output states.
Section 43. High-Speed PWM 43.15 EXTERNAL CONTROL OF INDIVIDUAL TIME BASE(S) (CURRENT RESET MODE) External signals can reset the primary dedicated time bases, if the XPRES bit (PWMCONx<1>) is set. This mode of operation is called Current Reset PWM mode. If the user-assigned application sets the Independent Time Base Mode bit, ITB (PWMCONx<9>), a PWM generator operates in Independent Time Base mode.
dsPIC33F/PIC24H Family Reference Manual Figure 43-46: Complementary PWM Output Mode Duty Cycle Match Dead Time(1) Dead Time(1) Timer Resets Period Value Dead Time(1) Timer Value PWM1H PWM1L 0 PWMxH Period Duty Cycle Period Note 1: Positive Dead Time shown. PWMxL (Period-duty cycle) Series Resonant/LLC Half-Bridge Converter Synchronous Buck Converter L1 VOUT +VIN +VIN PWM1H CR LR T1 VOUT + PWM1L DS70323E-page 43-94 + PWM1H PWM1L © 2008-2012 Microchip Technology Inc.
Section 43. High-Speed PWM 43.16.2 Push-Pull PWM Output Mode The Push-Pull PWM Output mode, illustrated in Figure 43-47, alternately outputs the PWM signal on one of two PWM pins. In this mode, complementary PWM output is not available. This mode is useful in transformer-based power converter circuits that avoid flow of direct current that saturates their cores. Push-Pull mode ensures that the duty cycle of the two phases is identical, thereby yielding a net DC bias of zero.
dsPIC33F/PIC24H Family Reference Manual 43.16.3 Multi-Phase PWM The Multi-Phase PWM, illustrated in Figure 43-48, uses phase shift values in the PHASEx registers to shift the PWM outputs with respect to the primary time base. Because the phase shift values are added to the primary time base, the phase shifted outputs occur earlier than a PWM signal that specifies zero phase shifts. In Multi-Phase mode, the specified phase shift is fixed by the design of the application.
Section 43. High-Speed PWM Figure 43-49: Interleaved PFC Diagram ILoad ID1 IL1 IIN PWM1 Ic ID2 IL2 PFC Output 90V - 265V Rectifier IS1 PWM2 IS2 43 Figure 43-50: Interleaved PFC Operational Waveforms PWM1 PWM2 PWM2 IL1 IL1 IL2 IL2 (IL1 + IL2) (IL1 + IL2) When duty cycle is > 50% © 2008-2012 Microchip Technology Inc.
dsPIC33F/PIC24H Family Reference Manual 43.16.4 Variable Phase PWM The Variable Phase PWM, illustrated in Figure 43-51, constantly changes the phase shift among PWM channels to control the flow of power, which is in contrast with most PWM circuits that vary the duty cycle of PWM signal to control power flow. In variable phase applications, the PWM duty cycle is often maintained at 50 percent. The phase shift value is available to all PWM modes that use the master time base.
Section 43. High-Speed PWM 43.16.5 Current Reset PWM The Current Reset PWM, illustrated in Figure 43-52, is a variable frequency mode where the actual PWM period is less than or equal to the specified period value. The independent time base is reset externally after the PWM signal has been deasserted. The Current Reset PWM mode can be used in Constant PWM On-Time mode. To operate in PWM Current Reset, the PWM generator must be in Independent Time Base.
dsPIC33F/PIC24H Family Reference Manual Figure 43-52: Current Reset PWM Programmed Period External Reset Period Value Duty Cycle PWMxH/L Duty Cycle Duty Cycle Programmed Period PWMxH/L Duty Cycle Duty Cycle New Period External current comparator resets PWM counter. PWM cycle restarts earlier than the programmed period. This is a Constant On-Time Variable Frequency PWM mode.
Section 43. High-Speed PWM 43.16.6 Constant Off-Time PWM Constant Off-Time PWM illustrated in Figure 43-53, is a variable-frequency PWM output where the actual PWM period is less than or equal to the specified period value. The PWM time base resets externally after the PWM signal duty cycle value is reached and the PWM signal is deasserted. This is implemented by enabling the On-Time PWM output called Current Reset PWM and using the complementary PWM output (PWMxL).
dsPIC33F/PIC24H Family Reference Manual Figure 43-54: Current-Limit PWM FLTx Negates PWM FLTx Negates PWM Period Value Duty Cycle 0 Programmed Period PWMxH/L Programmed Duty Cycle Programmed Duty Cycle PWMxH/L Actual Duty Cycle Actual Duty Cycle L D IL VOUT + COUT S ˜ PWM Current-Limit Current-Limit Programmed Duty Cycle PWMxH/L IL New Duty Cycle PWMxH/L DS70323E-page 43-102 © 2008-2012 Microchip Technology Inc.
Section 43. High-Speed PWM 43.17 BURST MODE IMPLEMENTATION In applications where the load current drawn from the converter is much smaller than its nominal current/converter operating at no load, the power drawn from the source can be reduced by forcing the converter into Discontinuous mode. This is achieved by deasserting the PWM outputs for a specific amount of time using the manual override feature.
dsPIC33F/PIC24H Family Reference Manual The scenario previously described can be prevented by using the flexible ADC triggering features of the High-Speed PWM module. The Special Event Trigger, primary PWM trigger and secondary PWM trigger can be used to generate an ADC conversion request with no software overhead. This feature guarantees that the ADC conversion is triggered exactly when needed by the circuitry.
Section 43. High-Speed PWM 43.18.3 PWM – Interrupt Controller Interconnect 43.18.3.1 PWM INTERRUPTS PWM Interrupts can be generated based on either a PWM fault, current-limit or trigger event. This feature is useful when certain software needs to be executed every time such an event occurs. For example, the PWM Interrupt service routine may contain the fault handling routine that should be executed after the PWM has been turned OFF.
dsPIC33F/PIC24H Family Reference Manual Figure 43-56: Staggering of CPU Load PWM2 Trigger PWM1 Trigger PWM1 Trigger PWM2 Trigger PWM1 Trigger PWM2 Trigger PWM2H PWM2L PWM1H PWM1L Execute First Control Loop Sample and Convert AN0 and AN1 (Pair 0) Idle Loop Execute Second Control Loop Sample and Convert AN2 and AN3 (Pair 1) DS70323E-page 43-106 Execute First Control Loop Execute First Control Loop Idle Loop Sample Idle and Loop Convert AN0 and AN1 (Pair 0) Execute Second Control Loop Sample
© 2008-2012 Microchip Technology Inc. 43.19 REGISTER MAP Table 43-8 and Table 43-9 map the bit functions for the High-Speed PWM control registers.
High-Speed PWM Register Map for Devices without Remappable I/O File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 PTCON PTEN — PTSIDL SESTAT SEIEN EIPU PTCON2 — — — — — — Bit 9 Bit 8 — — — Bit 5 Bit 4 Bit 3 — — SYNCSRC<2:0> — — Bit 2 Bit 1 Bit 0 SEVTPS<3:0> 0000 FFF8 SEVTCMP<12:0> STCON — — — SESTAT SEIEN EIPU STCON2 — — — — — — — SYNCPOL SYNCOEN SYNCEN — — STPER — SYNCSRC<2:0> — — — — SEVTPS<3:0> — — PCLKDIV<2:0> 0000 FFF8 SSEVTCMP<12:0> C
Section 43. High-Speed PWM 43.20 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC33F/PIC24H product family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the High-Speed PWM module are: Title Application Note # No related application notes are available at this time.
dsPIC33F/PIC24H Family Reference Manual 43.21 REVISION HISTORY Revision A (February 2008) This is the initial released version of the document Revision B (September 2008) This revision incorporates the following updates: • Equations: - Updated Equation 43-4 in 43.6 “PWM Generator” - Updated Equation 43-5 in 43.6.2.3 “Secondary Duty Cycle (SDCx)” • Examples: - Added an example for PWM Clock Code in 43.5.1 “PWM Clock Selection” • Figures: - Updated the labels in Figure 43-6 - Included new figure in 43.6.
Section 43. High-Speed PWM Revision C (March 2010) © 2008-2012 Microchip Technology Inc.
dsPIC33F/PIC24H Family Reference Manual Revision C (March 2010) (Continued) - Added a Note on power-saving modes, in 43.14.2 “High-Speed PWM Operation in Idle Mode” - Updated the Note in 43.16.5 “Current Reset PWM” • Registers: - Updated the register description for “PWMCAPx: Primary PWM Time Base Capture Register”, in 43.
Section 43. High-Speed PWM Revision C (March 2010) (Continued) • • • © 2008-2012 Microchip Technology Inc. DS70323E-page 43-113 43 High-Speed PWM • - Updated the following changes in 43.10.4 “Fault Exit”: • Removed the following description: The next PWM cycle begins when the PTMR value is zero • Updated step “c)” - Corrected the term “FSTAT” as “FLTSTAT” in 43.10.5 “Fault Exit with PMTMR Disabled” - Updated the following changes in 43.10.
dsPIC33F/PIC24H Family Reference Manual Revision D (March 2011) This revision includes the following updates: • Updated the definitions for the PTCON2, PHASEx, and SPHASEx registers in 43.
Section 43. High-Speed PWM Revision E (July 2012) This revision incorporates the following updates: © 2008-2012 Microchip Technology Inc. DS70323E-page 43-115 43 High-Speed PWM • Examples: - Updated 8 MHz to 7.37 MHz, and updated 120 MHz to 117.9 MHz, in Example 43-2 • Equations: - Added Equation title for Equation 43-1 through Equation 43-3 - Updated 1.04 ns to 1.06 ns in “The maximum PWM Duty Cycle resolution is 1.
dsPIC33F/PIC24H Family Reference Manual Revision E (July 2012) (Continued) • Sections: - Updated “The SYNCO signal pulse 200 ns ensures that other devices reliably sense the signals” to “The SYNCO signal pulse is 12 TCY clocks wide (about 300 ns at 40 MIPS) to ensure other devices can sense the signal”, in 43.5.6 “Time Base Synchronization” - Replaced Least Significant Byte (LSB) with LSb in 43.6.2.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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