Information
Table Of Contents
- TABLE 1: Silicon DEVREV Values (Continued)
- TABLE 2: Silicon Issue Summary (Continued)
- Silicon Errata Issues
- 1. Module: I/O Multiplexer
- 2. Module: CPU
- 3. Module: CPU
- 4. Module: PPS
- 5. Module: SPI
- 6. Module: SPI
- 7. Module: PWM
- 8. Module: PWM
- 9. Module: Power System
- 10. Module: Reserved
- 11. Module: ECAN™
- 12. Module: ECAN
- 13. Module: USB
- 14. Module: USB
- 15. Module: DMA
- 16. Module: UART
- 17. Module: UART
- 18. Module: UART
- 19. Module: I2C™
- 20. Module: ADC
- 21. Module: PMP
- 22. Module: Flash Memory
- 23. Module: Flash Memory
- 24. Module: Power System
- 25. Module: PWM
- 26. Module: QEI
- 27. Module: QEI
- 28. Module: CPU
- 29. Module: PWM
- 30. Module: ECAN
- 31. Module: Auxiliary Flash
- 32. Module: Auxiliary Flash
- 33. Module: Output Compare
- 34. Module: ADC
- Data Sheet Clarifications
- Appendix A: Revision History
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS80526C-page 8 © 2011-2012 Microchip Technology Inc.
10. Module: Reserved
11. Module: ECAN™
The CANCKS (CiCTRL1<11>) function is
reversed.
Work around
Set CiCTRL1<CANCKS> = 0 to obtain an FCAN
equal to twice FCY or CiCTRL1<CANCKS> = 1 to
obtain an FCAN equal to FCY. This bit must be set
to ‘1’ for compatibility with the dsPIC33F or
PIC24H. At reset it is set to ‘0’.
Affected Silicon Revisions
12. Module: ECAN
The ERRIF status flag (CiINTF<5>) does not get
set when a CAN error condition occurs, and as a
result, an interrupt is not generated even if
enabled.
Work around
Use the Invalid Message Interrupt (IVRIF) to
inspect the individual error condition status flags
TXBO, TXBP, RXBP, TXWAR, RXWAR and
EWARN (CiINTF<13:8>) to determine if an error
condition has occurred.
Affected Silicon Revisions
13. Module: USB
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the host may persistently drive the bus to an SE0
state (both D+/D- as ‘0’), which would be
interpreted as a bus Reset condition by the hub; or
the host may persistently drive the bus to a J state,
which would make the hub detach condition
undetectable by the host.
Work around
Connect low-speed devices directly to the Host
USB port and not through a USB hub.
Affected Silicon Revisions
14. Module: USB
In the case where the bus has been idle for > 3 ms,
and the UIDLE interrupt flag is set, if software
clears the interrupt flag, and the bus remains idle,
the UIDLE interrupt flag will not be set again.
Work around
Software can leave the UIDLE bit set until it has
received some indication of bus resumption.
(Resume, Reset, SOF, or Error).
Affected Silicon Revisions
B1
X
B1
X
B1
X
Note: Resume and Reset are the only interrupts
that should occur following UIDLE
assertion. If, at any point in time, the
UIDLE bit is set, it should be okay to
suspend the USB module (as long as this
code is protected by the GUARD and/or
ACTPEND logic). Note that this will
require software to clear the UIDLE
interrupt enable bit to exit the USB ISR (if
using interrupt driven code).
B1
X