Information

© 2011-2012 Microchip Technology Inc. DS80526C-page 9
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
15. Module: DMA
When the DMA is set up for CAN receive,
interrupts can sometimes be lost if the DMA is held
in an “OFF” state by the system arbiter. If a CAN
receive interrupt occurs while the DMA is waiting
for a grant for the previous CAN transaction, this
current interrupt will be dropped.
Work arounds
There are two possible work arounds for this issue:
1. Use Dual Port RAM (If available) for target
DMA memory; the DMA cannot be held
“OFF” when accessing the back side of
DPRAM. Only channels set up for CAN
receive would need to use DPRAM; all
other peripherals can use any RAM.
2. Elevate the system priority of DMA by writ-
ing a 0x20 to the MSTRPR (Master Priority)
SFR register (address 0x0058). This will
also prevent the DMA from being held
“OFF”.
Affected Silicon Revisions
16. Module: UART
When using UTXISEL = 01 (Interrupt when last
character is shifted out of the Transmit Shift
Register), and the final character is being shifted
out through the Transmit Shift Register, the TX
interrupt may occur before the final bit is shifted
out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete,
after which the following work around can be
implemented:
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
transmit shift register empty bit, as shown in
Example 2.
Affected Silicon Revisions
EXAMPLE 2:
B1
X
B1
X
// in UART2 initialization code
...
U2STAbits.UTXISEL0 = 1; // Set to generate TX interrupt when all
U2STAbits.UTXISEL1 = 0; // transmit operations are complete.
...
U2TXInterrupt(void)
{
while(U2STAbits.TRMT==0); // wait for the transmit buffer to be empty
... // process interrupt