Information

© 2011-2012 Microchip Technology Inc. DS80526C-page 13
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
30. Module: ECAN
When DMA is used with the ECAN module and the
CPU and DMA write to a ECAN special function
register (SFR) at the same time, the DMAC Error
trap is not occurring. In addition, neither the
PWCOLx bit of the DMAPWC SFR or the
DMACERR bit of the INTCON1 SFR are being set.
Since the PWCOLx bit is not set, subsequent DMA
requests to that channel are not ignored.
Work around
There is no work around; however, under normal
circumstances, this situation should not arise.
When DMA is used with the ECAN module, the
application should not be writing to the ECAN
SFRs.
Affected Silicon Revisions
31. Module: Auxiliary Flash
When a device is set to obtain the reset instruction
from Auxiliary Flash location 0x7FFFFC
(RSTPRI = 0) and Auxiliary Flash code protection
is enabled using the FAS register, the device does
not execute the application code after a Reset.
This configuration causes a Security Trap resulting
in a Reset.
Work around
The work around is dependent on errata issue 22
(Flash Memory) provided that the application will
accept both segments being code protected. The
Auxiliary Flash Reset Vector (RSTPRI = 0) does
function when code protection for the Auxiliary
Segment is not enabled using the FAS register.
Enabling code protection on the General Segment
using the FGS register protects the General
Segment and, because of errata issue 22, the
Auxiliary Segment is protected as well.
Affected Silicon Revisions
32. Module: Auxiliary Flash
When executing code in the Auxiliary Segment, all
interrupts and traps should vector through the
single auxiliary interrupt vector located at address
0x7FFFFA; however, the Address Error trap is not.
Instead, it vectors to the Address Error Trap vector
located at address 0x000006 in the General
Segment.
Work around
There is no universal work around. In a Bootloader
application, if the General Segment is erased and
an address error trap occurs, a Reset will result. If
the application routinely executes code from both
segments, the error address trap could then be
made to handle either circumstance. A flag could
be set to indicate code is executing from the
Auxiliary Segment and tested by the address error
trap handler.
Affected Silicon Revisions
33. Module: Output Compare
Under certain circumstances, an Output Compare
match may cause the interrupt flag (OCxIF) to
become set prior to the change of state of the OCx
pin. This has been observed when all of the
following are true:
• The module is in One-Shot mode (OCM<2:0>
= 001, 010 or 100);
• One of the timer modules is being used as the
time base; and
• A timer prescaler other than 1:1 is selected
If the module is reinitialized by clearing OCM<2:0>
after the One-Shot compare, the OCx pin may not
be driven as expected.
Work around
After OCxIF is set, allow an interval (in CPU
cycles) of at least twice the prescaler factor to
elapse before clearing OCM<2:0>. For example,
for a prescaler value of 1:8, allow 16 CPU cycles
to elapse after the interrupt.
Affected Silicon Revisions
B1
X
B1
X
B1
X
B1
X