Information

© 2011-2012 Microchip Technology Inc. DS80526C-page 11
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
23. Module: Flash Memory
The processor stalls while performing Run-Time
Self-Programming (RTSP) erase and write
operations on the same Flash segment (General or
Auxiliary) from which code is being executed. The
stall mechanism does not always function properly
and can cause unexpected behavior.
Work around
s
Two options are available to avoid this issue:
1. If you are required to execute code, includ-
ing an Interrupt Service Routine (ISR), from
the same segment (either General or Auxil-
iary) that you are performing RTSP opera-
tions on, you must disable interrupts until
the erase or programming operation is
complete (see Example 3).
2. If possible, structure your project such that
RTSP operations are performed on a seg-
ment from which no code is being executed.
For example, place all of your executable
code in the General Segment and all repro-
grammable data in the Auxiliary Segment or
vice versa. This solution has the added
advantage that no CPU stalls occur since
the programming operation is not being
performed on the same segment that is
executing the code.
EXAMPLE 3:
Affected Silicon Revisions
24. Module: Power System
The VREGSF bit functions as documented, but will
always read as ‘0’. Because of the Read-Modify-
Write process, any BSET or BCLR instruction of the
RCON register will also write a ‘0’ to the VREGSF
bit.
Work around
If the VREGSF bit is intended to be set to a ‘1’, the
user must also write a ‘1’ to the VREGSF bit when
setting or clearing any other bit in the RCON
register.
Affected Silicon Revisions
25. Module: PWM
When operating in Edge-Aligned Complimentary
mode, if the duty cycle (PDCx) becomes less than
the alternate dead time (ALTDTRx), the dead time
on the PWMs will become zero.
Work around
Ensure that the duty cycle (PDCx) always meets
the following condition: PDCx > (ALTDTRx - 1)
Affected Silicon Revisions
26. Module: QEI
In Quadrature Encoder mode (QEIxCON<CMM> =
00), the index counter registers (INDXxCNTH and
INDXxCNTL) cannot be relied upon to increment
when the last known direction was positive and an
index pulse occurs. The index register can
decrement even if the last known direction was
positive. This does not apply to external clock or
internal timer QEI modes.
Work around
The Index Event can be used to implement a
software counter. The direction could be
determined by comparing the current POSxCNT
value to that of the previous Index Event.
Affected Silicon Revisions
B1
X
; Load write latches if programming
…
; Setup NVMCON register to erase or program
as required
…
; Disable interrupts
PUSH SR
MOV #0x00E0, W0
IOR SR
; Write the KEY sequence
MOV #0x55, W0
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
; Start the programming sequence
BSET NVMCON, #15
; Insert two NOPs after programming
NOP
NOP
; Wait for operation to complete
prog_wait:
BTSC NVMCON, #15
BRA prog_wait
; Re-enable interrupts,
POP SR
B1
X
B1
X
B1
X