Datasheet

 2009-2012 Microchip Technology Inc. DS70616G-page 39
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
3.5 Programmer’s Model
The programmer’s model is shown in Figure 3-2. All
registers in the programmer’s model are memory
mapped and can be manipulated directly by
instructions. Table 3-1 lists a description of each
register.
In addition to the registers contained in the
programmer’s model, all devices in this family
contain control registers for interrupts, while
the dsPIC33EPXXX(GP/MC/MU)806/810/814 devices
contain control registers for Modulo and Bit-reversed
Addressing. These registers are described in
subsequent sections of this document.
All registers associated with the programmer’s model
are memory mapped, as shown in Table 4-1.
TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS
Register(s) Name Description
W0 through W15 Working Register Array
ACCA, ACCB 40-Bit DSP Accumulators
PC 23-Bit Program Counter
SR ALU and DSP Engine Status register
SPLIM Stack Pointer Limit Value register
TBLPAG Table Memory Page Address register
DSRPAG Extended Data Space (EDS) Read Page register
DSWPAG Extended Data Space (EDS) Write Page register
RCOUNT REPEAT Loop Count register
DCOUNT
(1)
DO Loop Count register
DOSTARTH
(1,2)
, DOSTARTL
(1,2)
DO Loop Start Address register (High and Low)
DOENDH
(1)
, DOENDL
(1)
DO Loop End Address register (High and Low)
CORCON Contains DSP Engine, DO Loop Control and Trap Status bits
Note 1: This register is available on dsPIC33EPXXX(GP/MC/MU)806/810/814 devices only.
2: The DOSTARTH and DOSTARTL registers are read-only.