Datasheet

 2009-2012 Microchip Technology Inc. DS70616G-page 29
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
VBUS
(4,6)
VUSB3V3
(4)
VBUSON
(4)
D+
(4,6)
D-
(4,6)
USBID
(4)
USBOEN
(4)
VBUSST
(4)
VCPCON
(4)
VCMPST1
(4)
VCMPST2
(4)
VCMPST3
(4)
VMIO
(4)
VPIO
(4)
DMH
(4)
DPH
(4)
DMLN
(4)
DPLN
(4)
RCV
(4)
I
P
O
I/O
I/O
I
O
I
O
I
I
I
I/O
I/O
O
O
O
O
I
Analog
—
—
Analog
Analog
ST
—
ST
—
ST
ST
ST
ST
ST
—
—
—
—
ST
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
USB bus power monitor.
USB internal transceiver supply. If the USB module is not being used,
this pin must be connected to V
DD.
USB host and On-The-Go (OTG) bus power control output.
D+ pin of internal USB transceiver.
D- pin of internal USB transceiver.
USB OTG ID detect.
USB output enabled control (for external transceiver).
USB boost controller overcurrent detection.
USB boost controller PWM signal.
USB External Comparator 1 input.
USB External Comparator 2 input.
USB External Comparator 3 input.
USB differential minus input/output (external transceiver).
USB differential plus input/output (external transceiver).
D- external pull-up control output.
D+ external pull-up control output.
D- external pull-down control output.
D+ External Pull-down Control Output.
USB receive input (from external transceiver).
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P ST No
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AV
DD
(2)
P P No Positive supply for analog modules. This pin must be connected at all
times.
AVSS P P No Ground reference for analog modules.
V
DD P — No Positive supply for peripheral logic and I/O pins.
V
CAP P — No CPU logic filter capacitor connection.
V
SS P — No Ground reference for logic and I/O pins.
V
REF+ I Analog No Analog voltage reference (high) input.
V
REF- I Analog No Analog voltage reference (low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select TTL = TTL input buffer
Note 1: This pin is available on dsPIC33EPXXX(MC/MU)806/810/814 devices only.
2: AV
DD must be connected at all times.
3: These pins are input only on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices.
4: These pins are only available on dsPIC33EPXXXMU8XX and PIC24EPXXXGU8XX devices.
5: The availability of I
2
C™ interfaces varies by device. Refer to the “Pin Diagrams” section for availability.
Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits, ALTI2C1 and
ALTI2C2 (FPOR<5:4>). See Section 29.0 “Special Features” for more information.
6: Analog functionality is activated by enabling the USB module and is not controlled by the ANSEL register.