Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 276  2009-2012 Microchip Technology Inc.
FIGURE 13-1: TYPE B TIMERx BLOCK DIAGRAM (x = 2, 4, 6 AND 8)
FIGURE 13-2: TYPE C TIMERx BLOCK DIAGRAM (x = 3, 5, 7 AND 9)
TGATE
TCS
00
10
x1
TMRx
PRx
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
FP
(1)
Prescaler
(/n)
TCKPS<1:0>
Note 1: FP is the peripheral clock.
Latch
Data
CLK
TxCLK
Gate
Sync
Falling Edge
Detect
Sync
Prescaler
(/n)
Comparator
TGATE
TCS
00
10
x1
Comparator
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
Gate
Sync
F
P
(1)
Falling Edge
Detect
Prescaler
(/n)
TCKPS<1:0>
Note 1: FP is the peripheral clock.
2: The ADC trigger is available on TMR3 and TMR5 only.
Latch
Data
CLK
TxCLK
ADC Start of
Conversion Trigger
(2)
Prescaler
(/n)
Sync
TMRx
PRx