Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 180  2009-2012 Microchip Technology Inc.
Figure 9-3 illustrates a block diagram of the auxiliary
PLL module.
FIGURE 9-3: APLL BLOCK DIAGRAM
Equation 9-4 shows the relationship between the
auxiliary PLL input clock frequency (F
AIN) and the
AVCO frequency (FAVCO).
EQUATION 9-4: FAVCO CALCULATION
Note: The auxiliary PLL module is only avail-
able on dsPIC33EPXXXMU8XX and
PIC24EPXXXGU8XX devices.
÷ N1
÷ M
PFD VCO
APLLPRE<2:0>
APLLDIV <2:0>
3 MHz < FAREF < 5.5 MHz
60 MH
Z < FAVCO < 120 MHZ
FAIN
FAREF FAVCO
FAVCO FAIN
M
N1
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

=