Datasheet

 2009-2012 Microchip Technology Inc. DS70616G-page 551
dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
TABLE 32-49: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  T
A  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param. Symbol Characteristic
(4)
Min.
(1)
Max. Units Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode T
CY/2 (BRG + 2) — s
1 MHz mode
(2)
TCY/2 (BRG + 2) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode T
CY/2 (BRG + 2) — s
1 MHz mode
(2)
TCY/2 (BRG + 2) — s
IM20 TF:SCL SDAx and SCLx
Fall Time
100 kHz mode — 300 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
1 MHz mode
(2)
— 100 ns
IM21 TR:SCL SDAx and SCLx
Rise Time
100 kHz mode — 1000 ns CB is specified to be
from 10 to 400 pF
400 kHz mode 20 + 0.1 C
B 300 ns
1 MHz mode
(2)
— 300 ns
IM25 TSU:DAT Data Input
Setup Time
100 kHz mode 250 — ns
400 kHz mode 100 — ns
1 MHz mode
(2)
40 — ns
IM26 THD:DAT Data Input
Hold Time
100 kHz mode 0 — s
400 kHz mode 0 0.9 s
1 MHz mode
(2)
0.2 — s
IM30 TSU:STA Start Condition
Setup Time
100 kHz mode TCY/2 (BRG + 2) — s Only relevant for
Repeated Start
condition
400 kHz mode T
CY/2 (BRG + 2) — s
1 MHz mode
(2)
TCY/2 (BRG + 2) — s
IM31 THD:STA Start Condition
Hold Time
100 kHz mode TCY/2 (BRG + 2) — s After this period, the
first clock pulse is
generated
400 kHz mode T
CY/2 (BRG +2) — s
1 MHz mode
(2)
TCY/2 (BRG + 2) — s
IM33 TSU:STO Stop Condition
Setup Time
100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode T
CY/2 (BRG + 2) — s
1 MHz mode
(2)
TCY/2 (BRG + 2) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s
Hold Time 400 kHz mode T
CY/2 (BRG + 2) — s
1 MHz mode
(2)
TCY/2 (BRG + 2) — s
IM40 T
AA:SCL Output Valid
From Clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode
(2)
— 400 ns
IM45 T
BF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — s
1 MHz mode
(2)
0.5 — s
IM50 C
B Bus Capacitive Loading — 400 pF
IM51 T
PGD Pulse Gobbler Delay 65 390 ns See Note 3
Note 1: BRG is the value of the I
2
C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I
2
C™)”
(DS70330) in the “dsPIC33E/PIC24E Family Reference Manual”. Please see the Microchip web site for
the latest family reference manual sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
4: These parameters are characterized, but not tested in manufacturing.