Datasheet

dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814
DS70616G-page 480  2009-2012 Microchip Technology Inc.
JTAGEN FICD ImmediateJTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
RSTPRI FICD On any
device Reset
Reset Target Vector Select bit
1 = Device will reset to Primary Flash Reset location
0 = Device will reset to Auxiliary Flash Reset location
ICS<1:0> FICD Immediate ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
TABLE 29-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Register RTSP Effect Description
Note 1: BOR should always be enabled for proper operation (BOREN = 1).
2: This register can only be modified when code protection and write protection are disabled for both the
General and Auxiliary Segments (APL = 1, AWRP = 1, APLK = 0, GSS = 1, GWRP = 1 and GSSK = 0).