Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 28 16-Bit 70 null I/O number 21

100

 2011-2013 Microchip Technology Inc. DS70000657H-page 97

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X

TABLE 4-42: OP AMP/COMPARATOR REGISTER MAP

TABLE 4-44: JTAG INTERFACE REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

CMSTAT 0A80 PSIDL

— — — C4EVT C3EVT C2EVT C1EVT — — — — C4OUT C3OUT C2OUT C1OUT 0000

CVRCON 0A82

—CVR2OE — — — VREFSEL — — CVREN CVR1OE CVRR CVRSS CVR<3:0> 0000

CM1CON 0A84 CON COE CPOL

— — OPMODE CEVT COUT EVPOL<1:0> — CREF — —CCH<1:0>0000

CM1MSKSRC 0A86

— — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000

CM1MSKCON 0A88 HLMS

— OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000

CM1FLTR 0A8A

— — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000

CM2CON 0A8C CON COE CPOL

— — OPMODE CEVT COUT EVPOL<1:0> — CREF — —CCH<1:0>0000

CM2MSKSRC 0A8E

— — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000

CM2MSKCON 0A90 HLMS

— OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000

CM2FLTR 0A92

— — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000

CM3CON

(1)

0A94 CON COE CPOL — — OPMODE CEVT COUT EVPOL<1:0> — CREF — —CCH<1:0>0000

CM3MSKSRC

(1)

0A96 — — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000

CM3MSKCON

(1)

0A98 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000

CM3FLTR

(1)

0A9A — — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000

CM4CON 0A9C CON COE CPOL

— — — CEVT COUT EVPOL<1:0> — CREF — —CCH<1:0>0000

CM4MSKSRC 0A9E

— — — — SELSRCC<3:0> SELSRCB<3:0> SELSRCA<3:0> 0000

CM4MSKCON 0AA0 HLMS

— OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN 0000

CM4FLTR 0AA2

— — — — — — — — — CFSEL<2:0> CFLTREN CFDIV<2:0> 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: These registers are unavailable on dsPIC33EPXXXGP502/MC502/MC202 and PIC24EP256GP/MC202 (28-pin) devices.

TABLE 4-43: CTMU REGISTER MAP

File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

CTMUCON1 033A CTMUEN

— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000

CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0>

— — 0000

CTMUICON 033E ITRIM<5:0> IRNG<1:0>

— — — — — — — — 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

JDATAH 0FF0

— — — — JDATAH<27:16> xxxx

JDATAL 0FF2 JDATAL<15:0> 0000

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.