Datasheet

 2011-2013 Microchip Technology Inc. DS70000657H-page 447
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-47: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  T
A  +125°C for Extended
Param. Symbol Characteristic
(1)
Min. Typ.
(2)
Max. Units Conditions
SP70 FscP Maximum SCK1 Input Frequency — — 15 MHz (Note 3)
SP72 TscF SCK1 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK1 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO1 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO1 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI1 Data Input
to SCK1 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS1
 to SCK1  or SCK1 
Input
120 — — ns
SP51 TssH2doZ SS1  to SDO1 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH,
TscL2ssH
SS1
after SCK1 Edge 1.5 TCY + 40 — — ns (Note 4)
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI1 pins.