Datasheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 42 2011-2013 Microchip Technology Inc.
REGISTER 3-2: CORCON: CORE CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR
—US1
(1)
US0
(1)
EDT
(1,2)
DL2
(1)
DL1
(1)
DL0
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0
SATA
(1)
SATB
(1)
SATDW
(1)
ACCSAT
(1)
IPL3
(3)
SFA RND
(1)
IF
(1)
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing latency is enabled
0 = Fixed exception processing latency is enabled
bit 14 Unimplemented: Read as ‘0’
bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits
(1)
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit
(1,2)
1 = Terminates executing DO loop at end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
(1)
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
bit 7 SATA: ACCA Saturation Enable bit
(1)
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit
(1)
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
(1)
1 = Data Space write saturation is enabled
0 = Data Space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
(1)
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3
(3)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2: This bit is always read as ‘0’.
3: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.