Datasheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 304 2011-2013 Microchip Technology Inc.
REGISTER 21-17: CxRXFnEID: ECANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER
REGISTER (n = 0-15)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 15 bit 8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 EID<15:0>: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
0 = Message address bit, EIDx, must be ‘0’ to match filter
REGISTER 21-18: CxFMSKSEL1:
ECAN
x
FILTER 7-0 MASK SELECTION REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F7MSK<1:0> F6MSK<1:0> F5MSK<1:0> F4MSK<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F3MSK<1:0> F2MSK<1:0> F1MSK<1:0> F0MSK<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bits
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bits<15:14>)
bit 11-10 F5MSK<1:0>: Mask Source for Filter 5 bits (same values as bits<15:14>)
bit 9-8 F4MSK<1:0>: Mask Source for Filter 4 bits (same values as bits<15:14>)
bit 7-6 F3MSK<1:0>: Mask Source for Filter 3 bits (same values as bits<15:14>)
bit 5-4 F2MSK<1:0>: Mask Source for Filter 2 bits (same values as bits<15:14>)
bit 3-2 F1MSK<1:0>: Mask Source for Filter 1 bits (same values as bits<15:14>)
bit 1-0 F0MSK<1:0>: Mask Source for Filter 0 bits (same values as bits<15:14>)