Datasheet

 2011-2013 Microchip Technology Inc. DS70000657H-page 159
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
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00001 = Input divided by 3
00000 = Input divided by 2 (default)
REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.