Datasheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 510 2011-2013 Microchip Technology Inc.
Revision F (November 2012)
Removed “Preliminary” from data sheet footer.
Revision G (March 2013)
This revision includes the following global changes:
• changes “FLTx
” pin function to “FLTx” on all
occurrences
• adds Section 31.0 “High-Temperature Electrical
Characteristics” for high-temperature (+150°C)
data
This revision also includes minor typographical and
formatting changes throughout the text.
Other major changes are referenced by their respective
section in Table A-5.
TABLE A-5: MAJOR SECTION UPDATES
Section Name Update Description
Cover Section • Changes internal oscillator specification to 1.0%
• Changes I/O sink/source values to 12 mA or 6 mA
• Corrects 44-pin VTLA pin diagram (pin 32 now shows as 5V tolerant)
Section 4.0 “Memory
Organization”
• Deletes references to Configuration shadow registers
• Corrects the spelling of the JTAGIP and PTGWDTIP bits throughout
• Corrects the Reset value of all IOCON registers as C000h
• Adds footnote to Ta bl e 4- 4 2 to indicate the absence of Comparator 3 in 28-pin
devices
Section 6.0 “Resets” • Removes references to cold and warm Resets, and clarifies the initial configuration of
the device clock source on all Resets
Section 7.0 “Interrupt
Controller”
• Corrects the definition of GIE as “Global Interrupt Enable” (not “General”)
Section 9.0 “Oscillator
Configuration”
• Clarifies the behavior of the CF bit when cleared in software
• Removes POR behavior footnotes from all control registers
• Corrects the tuning range of the TUN<5:0> bits in Register 9-4 to an overall range
±1.5%
Section 13.0 “Timer2/3 and
Timer4/5”
• Clarifies the presence of the ADC Trigger in 16-bit Timer3 and Timer5, as well as the
32-bit timers
Section 15.0 “Output
Compare”
• Corrects the first trigger source for SYNCSEL<4:0> (OCxCON2<4:0>) as OCxRS
match
Section 16.0 “High-Speed
PWM Module”
• Clarifies the source of the PWM interrupts in Figure 16-1
• Corrects the Reset states of IOCONx<15:14> in Register 16-13 as ‘
11’
Section 17.0 “Quadrature
Encoder Interface (QEI)
Module”
• Clarifies the operation of the IMV<1:0> bits (QEICON<9:8>) with updated text and
additional notes
• Corrects the first prescaler value for QFVDIV<2:0> (QEI1OC<13:11>), now 1:128
Section 23.0 “10-Bit/12-Bit
Analog-to-Digital Converter
(ADC)”
• Adds note to Figure 23-1 that Op Amp 3 is not available in 28-pin devices
• Changes “sample clock” to “sample trigger” in AD1CON1 (Register 23-1)
• Clarifies footnotes on op amp usage in Registers 23-5 and 23-6
Section 25.0 “Op Amp/
Comparator Module”
• Adds Note text to indicate that Comparator 3 is unavailable in 28-pin devices
• Splits Figure 25-1 into two figures for clearer presentation (Figure 25-1 for Op amp/
Comparators 1 through 3, Figure 25-2 for Comparator 4). Subsequent figures are
renumbered accordingly.
• Corrects reference description in xxxxx (now (AV
DD+AVSS)/2)
• Changes CMSTAT<15> in Register 25-1 to “PSIDL”
Section 27.0 “Special
Features”
• Corrects the addresses of all Configuration bytes for 512 Kbyte devices