Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 361
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL =
1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL =
0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity-selected comparator
output (while CEVT = 0)
If CPOL =
1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL =
0 (non-inverted polarity):
Low-to-high transition of the comparator output
00 = Trigger/event/interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Reference Select bit (VIN+ input)
(1)
1 = VIN+ input connects to internal CVREFIN voltage
(2)
0 = VIN+ input connects to CxIN1+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Op Amp/Comparator Channel Select bits
(1)
11 = Unimplemented
10 = Unimplemented
01 = Inverting input of the comparator connects to the CxIN2- pin
(2)
00 = Inverting input of the op amp/comparator connects to the CxIN1- pin
REGISTER 25-2: CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2 OR 3) (CONTINUED)
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2: This input is not available when OPMODE (CMxCON<10>) = 1.