Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 35

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X

3.5 Programmer’s Model

The programmer’s model for the

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,

and PIC24EPXXXGP/MC20X is shown in Figure 3-2.

All registers in the programmer’s model are memory

mapped and can be manipulated directly by

instructions. Tabl e 3- 1 lists a description of each

In addition to the registers contained in the

programmer’s model, the dsPIC33EPXXXGP50X,

dsPIC33EPXXXMC20X/50X, and PIC24EPXXXGP/

MC20X devices contain control registers for Modulo

Addressing (dsPIC33EPXXXMC20X/50X and

dsPIC33EPXXXGP50X devices only), Bit-Reversed

Addressing (dsPIC33EPXXXMC20X/50X and

dsPIC33EPXXXGP50X devices only) and interrupts.

These registers are described in subsequent

sections of this document.

All registers associated with the programmer’s model

are memory mapped, as shown in Tabl e 4- 1.

TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

W0 through W15 Working Register Array

ACCA, ACCB 40-Bit DSP Accumulators

PC 23-Bit Program Counter

SR ALU and DSP Engine STATUS Register

SPLIM Stack Pointer Limit Value Register

TBLPAG Table Memory Page Address Register

DSRPAG Extended Data Space (EDS) Read Page Register

DSWPAG Extended Data Space (EDS) Write Page Register

RCOUNT REPEAT Loop Count Register

DCOUNT

(1)

DO Loop Count Register

DOSTARTH

(1,2)

, DOSTARTL

(1,2)

DO Loop Start Address Register (High and Low)

DOENDH

(1)

, DOENDL

(1)

DO Loop End Address Register (High and Low)

CORCON Contains DSP Engine, DO Loop Control and Trap Status bits

Note 1: This register is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.

2: The DOSTARTH and DOSTARTL registers are read-only.