Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 291
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 21-4: CxFCTRL: ECANx FIFO CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
DMABS<2:0>
— — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — FSA<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 DMABS<2:0>: DMA Buffer Size bits
111 = Reserved
110 = 32 buffers in RAM
101 = 24 buffers in RAM
100 = 16 buffers in RAM
011 = 12 buffers in RAM
010 = 8 buffers in RAM
001 = 6 buffers in RAM
000 = 4 buffers in RAM
bit 12-5 Unimplemented: Read as ‘0’
bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits
11111 = Read Buffer RB31
11110 = Read Buffer RB30
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•
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00001 = TX/RX Buffer TRB1
00000 = TX/RX Buffer TRB0