Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 271
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
19.0 INTER-INTEGRATED
CIRCUIT™ (I
2
C™)
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X family of devices
contains two Inter-Integrated Circuit (I
2
C) modules:
I2C1 and I2C2.
The I
2
C module provides complete hardware support
for both Slave and Multi-Master modes of the I
2
C serial
communication standard, with a 16-bit interface.
The I
2
C module has a 2-pin interface:
• The SCLx pin is clock
• The SDAx pin is data
The I
2
C module offers the following key features:
•I
2
C interface supporting both Master and Slave
modes of operation
•I
2
C Slave mode supports 7 and 10-bit addressing
•I
2
C Master mode supports 7 and 10-bit addressing
•I
2
C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for I
2
C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control)
•I
2
C supports multi-master operation, detects bus
collision and arbitrates accordingly
• Intelligent Platform Management Interface (IPMI)
support
• System Management Bus (SMBus) support
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to Section 19. “Inter-Integrated
Circuit™ (I
2
C™)” (DS70330) of the
“dsPIC33E/PIC24E Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.