Datasheet

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 264  2011-2013 Microchip Technology Inc.
FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM
Internal Data Bus
SDIx
SDOx
SSx
/FSYNCx
SCKx
bit 0
Shift Control
Edge
Select
F
P
Primary
1:1/4/16/64
Enable
Prescaler
Sync
Control
TransferTransfer
Write SPIxBUFRead SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Note 1: In Standard mode, the FIFO is only one level deep.
Clock
Control
Secondary
Prescaler
1:1 to 1:8
SPIxSR
8-Level FIFO
Receive Buffer
(1)
8-Level FIFO
Transmit Buffer
(1)
SPIxBUF