Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 239
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to PWMxL pins; PWMxL output signal is connected to
PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base
0 = Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary
REGISTER 16-13: IOCONx: PWMx I/O CONTROL REGISTER
(2)
(CONTINUED)
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: If the PWMLOCK Configuration bit (FOSCSEL<6>) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.