Datasheet

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70657G-page 226  2011-2013 Microchip Technology Inc.
FIGURE 16-2: HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM
MUX
PTMRx
PDCx
PWMCONx,
PTCON, PTCON2
IOCONx
DTRx
PWMxL
PWMxH
FLTx
PWM1L
PWM1H
FCLCONx
MDC
PHASEx
LEBCONx,
ALTDTRx
User Override Logic
Current-Limit
PWM Output Mode
Control Logic
Logic
Pin
Control
Logic
Fault and
Current-Limit
Logic
PWM Generator 1
FLTx
PWM Generator 2 and PWM Generator 3
Interrupt
Logic
(1)
Module Control and Timing
Master Duty Cycle Register
Synchronization
Synchronization
Master PeriodMaster Period
Master Duty CycleMaster Duty Cycle
SYNCI1
SYNCO1
SEVTCMP
Comparator
Special Event Trigger
Special Event
Postscaler
PTPER
PMTMR
Primary Master Time Base
Master Time Base Counter
Special Event Compare Trigger
Comparator
Clock
Prescaler
Comparator
Dead-Time
Fault Override Logic
Override Logic
DTCMPx
DTCMP1
FOSC
PWMKEY
IOCONx and FCLCONx Unlock Register
AUXCONx
LEBDLYx
PTG Trigger
Input
PTG Trigger Input
PTG Trigger Input
TRGCONx
PWMCAPx
ADC Trigger
Comparator
TRIGx
16-Bit Data Bus
Note 1: The PWM interrupts are generated by logically ORing the FLTSTAT, CLSTAT and TRGSTAT status bits for the
given PWM generator. Refer to the “dsPIC33E/PIC24E Family Reference Manual”, Section 14. “High-Speed
PWM” (DS70645) for more information.