Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 517
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
CxBUFPNT4 (ECANx Filter 12-15
Buffer Pointer 4)................................................ 300
CxCFG1 (ECANx Baud Rate Configuration 1) ......... 296
CxCFG2 (ECANx Baud Rate Configuration 2) ......... 297
CxCTRL1 (ECANx Control 1) ................................... 288
CxCTRL2 (ECANx Control 2) ................................... 289
CxEC (ECANx Transmit/Receive Error Count)......... 296
CxFCTRL (ECANx FIFO Control)............................. 291
CxFEN1 (ECANx Acceptance Filter Enable 1) ......... 298
CxFIFO (ECANx FIFO Status).................................. 292
CxFMSKSEL1 (ECANx Filter 7-0
Mask Selection) ................................................ 302
CxFMSKSEL2 (ECANx Filter 15-8
Mask Selection) ................................................ 303
CxINTE (ECANx Interrupt Enable)............................ 295
CxINTF (ECANx Interrupt Flag) ................................ 293
CxRXFnEID (ECANx Acceptance Filter n
Extended Identifier)........................................... 302
CxRXFnSID (ECANx Acceptance Filter n
Standard Identifier) ........................................... 301
CxRXFUL1 (ECANx Receive Buffer Full 1) .............. 305
CxRXFUL2 (ECANx Receive Buffer Full 2) .............. 305
CxRXMnEID (ECANx Acceptance Filter Mask n
Extended Identifier)........................................... 304
CxRXMnSID (ECANx Acceptance Filter Mask n
Standard Identifier) ........................................... 304
CxRXOVF1 (ECANx Receive Buffer Overflow 1) ..... 306
CxRXOVF2 (ECANx Receive Buffer Overflow 2) ..... 306
CxTRmnCON (ECANx TX/RX Buffer mn Control).... 307
CxVEC (ECANx Interrupt Code) ............................... 290
DEVID (Device ID) .................................................... 381
DEVREV (Device Revision)...................................... 381
DMALCA (DMA Last Channel Active Status) ........... 148
DMAPPS (DMA Ping-Pong Status) .......................... 149
DMAPWC (DMA Peripheral Write
Collision Status)................................................ 146
DMARQC (DMA Request Collision Status) .............. 147
DMAxCNT (DMA Channel x Transfer Count) ........... 144
DMAxCON (DMA Channel x Control) ....................... 140
DMAxPAD (DMA Channel x Peripheral Address)..... 144
DMAxREQ (DMA Channel x IRQ Select) ................. 141
DMAxSTAH (DMA Channel x
Start Address A, High) ...................................... 142
DMAxSTAL (DMA Channel x
Start Address A, Low)....................................... 142
DMAxSTBH (DMA Channel x
Start Address B, High) ...................................... 143
DMAxSTBL (DMA Channel x Start
Address B, Low) ............................................... 143
DSADRH (DMA Most Recent RAM
High Address) ................................................... 145
DSADRL (DMA Most Recent RAM Low Address) .... 145
DTRx (PWMx Dead-Time) ........................................ 236
FCLCONx (PWMx Fault Current-Limit Control) ........ 241
I2CxCON (I2Cx Control) ........................................... 274
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 278
I2CxSTAT (I2Cx Status) ........................................... 276
ICxCON1 (Input Capture x Control 1)....................... 213
ICxCON2 (Input Capture x Control 2)....................... 214
INDXxCNTH (Index Counter High Word).................. 257
INDXxCNTL (Index Counter Low Word) ................... 257
INDXxHLD (Index Counter Hold) .............................. 258
INTCON1 (Interrupt Control 1).................................. 132
INTCON2 (Interrupt Control 2).................................. 134
INTCON2 (Interrupt Control 3).................................. 135
INTCON4 (Interrupt Control 4) ................................. 135
INTTREG Interrupt Control and Status Register ...... 136
INTxHLDH (Interval Timer Hold High Word) ............ 261
INTxHLDL (Interval Timer Hold Low Word).............. 261
INTxTMRH (Interval Timer High Word) .................... 260
INTxTMRL (Interval Timer Low Word)...................... 261
IOCONx (PWMx I/O Control).................................... 238
LEBCONx (PWMx Leading-Edge
Blanking Control).............................................. 243
LEBDLYx (PWMx Leading-Edge Blanking Delay).... 244
MDC (PWMx Master Duty Cycle)............................. 232
NVMADR (Nonvolatile Memory Lower Address)...... 120
NVMADRU (Nonvolatile Memory Upper Address) ... 120
NVMCON (Nonvolatile Memory (NVM) Control) ...... 119
NVMKEY (Nonvolatile Memory Key) ........................ 120
OCxCON1 (Output Compare x Control 1) ................ 219
OCxCON2 (Output Compare x Control 2) ................ 221
OSCCON (Oscillator Control)................................... 154
OSCTUN (FRC Oscillator Tuning)............................ 159
PDCx (PWMx Generator Duty Cycle)....................... 235
PHASEx (PWMx Primary Phase-Shift)..................... 235
PLLFBD (PLL Feedback Divisor) ............................. 158
PMD1 (Peripheral Module Disable Control 1) .......... 164
PMD2 (Peripheral Module Disable Control 2) .......... 166
PMD3 (Peripheral Module Disable Control 3) .......... 167
PMD4 (Peripheral Module Disable Control 4) .......... 167
PMD6 (Peripheral Module Disable Control 6) .......... 168
PMD7 (Peripheral Module Disable Control 7) .......... 169
POSxCNTH (Position Counter High Word) .............. 256
POSxCNTL (Position Counter Low Word)................ 256
POSxHLD (Position Counter Hold)........................... 256
PTCON (PWMx Time Base Control) ........................ 228
PTCON2 (PWMx Primary Master Clock
Divider Select) .................................................. 230
PTGADJ (PTG Adjust).............................................. 346
PTGBTE (PTG Broadcast Trigger Enable)............... 341
PTGC0LIM (PTG Counter 0 Limit) ........................... 344
PTGC1LIM (PTG Counter 1 Limit) ........................... 345
PTGCON (PTG Control)........................................... 340
PTGCST (PTG Control/Status) ................................ 338
PTGHOLD (PTG Hold)............................................. 345
PTGL0 (PTG Literal 0).............................................. 346
PTGQPTR (PTG Step Queue Pointer)..................... 347
PTGQUEx (PTG Step Queue x)............................... 347
PTGSDLIM (PTG Step Delay Limit) ......................... 344
PTGT0LIM (PTG Timer0 Limit) ................................ 343
PTGT1LIM (PTG Timer1 Limit) ................................ 343
PTPER (PWMx Primary Master Time Base
Period).............................................................. 231
PWMCONx (PWMx Control) .................................... 233
QEI1CON (QEI Control) ........................................... 250
QEI1GECH (Greater Than or Equal Compare
High Word) ....................................................... 260
QEI1GECL (Greater Than or Equal Compare
Low Word) ........................................................ 260
QEI1ICH (Initialization/Capture High Word) ............. 258
QEI1ICL (Initialization/Capture Low Word)............... 258
QEI1IOC (QEI I/O Control) ....................................... 252
QEI1LECH (Less Than or Equal Compare
High Word) ....................................................... 259
QEI1LECL (Less Than or Equal Compare
Low Word) ........................................................ 259
QEI1STAT (QEI Status) ........................................... 254
RCON (Reset Control).............................................. 123
REFOCON (Reference Oscillator Control) ............... 160