Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 515
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Interrupt Controller
Control and Status Registers .................................... 129
INTCON1 .......................................................... 129
INTCON2 .......................................................... 129
INTCON3 .......................................................... 129
INTCON4 .......................................................... 129
INTTREG .......................................................... 129
Interrupt Vector Details ............................................. 127
Interrupt Vector Table (IVT) ...................................... 125
Reset Sequence ....................................................... 125
Resources................................................................. 129
J
JTAG Boundary Scan Interface ........................................ 377
JTAG Interface.................................................................. 384
M
Memory Maps
Extended Data Space ............................................... 107
Memory Organization.......................................................... 43
Resources................................................................... 60
Microchip Internet Web Site.............................................. 520
Modulo Addressing ........................................................... 112
Applicability ............................................................... 113
Operation Example ................................................... 112
Start and End Address.............................................. 112
W Address Register Selection .................................. 112
MPLAB ASM30 Assembler, Linker, Librarian ................... 396
MPLAB Integrated Development
Environment Software............................................... 395
MPLAB PM3 Device Programmer .................................... 398
MPLAB REAL ICE In-Circuit Emulator System................. 397
MPLINK Object Linker/MPLIB Object Librarian ................ 396
O
Op Amp
Application Considerations ....................................... 356
Configuration A ................................................. 356
Configuration B ................................................. 357
Op Amp/Comparator......................................................... 353
Control Registers ...................................................... 358
Resources................................................................. 357
Open-Drain Configuration ................................................. 172
Oscillator
Control Registers ...................................................... 154
Resources................................................................. 153
Output Compare ............................................................... 217
Control Registers ...................................................... 219
Resources................................................................. 218
P
Packaging ......................................................................... 477
Details ....................................................................... 500
Marking ............................................................. 477, 479
Peripheral Module Disable (PMD) .................................... 163
Peripheral Pin Select (PPS).............................................. 173
Available Peripherals ................................................ 173
Available Pins ........................................................... 173
Control ...................................................................... 173
Control Registers ...................................................... 181
Input Mapping ........................................................... 174
Output Selection for Remappable Pins..................... 178
Pin Selection for Selectable Input Sources............... 176
Selectable Input Sources .......................................... 175
Peripheral Trigger Generator (PTG) Module .................... 335
Pinout I/O Descriptions (table) ............................................ 24
Power-Saving Features .................................................... 161
Clock Frequency....................................................... 161
Clock Switching ........................................................ 161
Instruction-Based Modes .......................................... 161
Idle.................................................................... 162
Interrupts Coincident with Power Save
Instructions............................................... 162
Sleep ................................................................ 162
Resources ................................................................ 163
Program Address Space..................................................... 43
Construction ............................................................. 115
Data Access from Program Memory Using
Table Instructions ............................................. 116
Data Access from, Address Generation ................... 115
Memory Map (dsPIC33EP128GP50X,
dsPIC33EP128MC20X/50X,
PIC24EP128GP/MC20X Devices).......................... 45
Memory Map (dsPIC33EP256GP50X,
dsPIC33EP256MC20X/50X,
PIC24EP256GP/MC20X Devices).......................... 46
Memory Map (dsPIC33EP32GP50X,
dsPIC33EP32MC20X/50X,
PIC24EP32GP/MC20X Devices)............................ 43
Memory Map (dsPIC33EP512GP50X,
dsPIC33EP512MC20X/50X,
PIC24EP512GP/MC20X Devices).......................... 47
Memory Map (dsPIC33EP64GP50X,
dsPIC33EP64MC20X/50X,
PIC24EP64GP/MC20X Devices)............................ 44
Table Read High Instructions
TBLRDH ........................................................... 116
Table Read Low Instructions (TBLRDL)................... 116
Program Memory
Organization ............................................................... 48
Reset Vector............................................................... 48
Programmable CRC Generator ........................................ 371
Control Registers...................................................... 373
Overview................................................................... 372
Resources ................................................................ 372
Programmer’s Model .......................................................... 35
Register Description ................................................... 35
PTG
Control Registers...................................................... 338
Introduction............................................................... 335
Output Descriptions .................................................. 351
Resources ................................................................ 337
Step Commands and Format ................................... 348
Q
QEI
Control Registers...................................................... 250
Resources ................................................................ 249
Quadrature Encoder Interface (QEI)................................. 247
R
Reader Response............................................................. 521
Register Maps
ADC1 .......................................................................... 82
CPU Core (dsPIC33EPXXXMC20X/50X,
dsPIC33EPXXXGP50X Devices) ....................... 61
CPU Core (PIC24EPXXXGP/MC20X Devices).......... 63
CRC............................................................................ 86
CTMU ......................................................................... 95
DMAC ......................................................................... 96