Datasheet

 2011-2013 Microchip Technology Inc. DS70657G-page 429
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
TABLE 30-37: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  T
A  +125°C for Extended
Param. Symbol Characteristic
(1)
Min. Typ.
(2)
Max. Units Conditions
SP70 FscP Maximum SCK2 Input
Frequency
— — Lesser
of FP
or 15
MHz (Note 3)
SP72 TscF SCK2 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK2 Input Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO2 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO2 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
— 6 20 ns
SP36 TdoV2scH,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30 — — ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP41 TscH2diL,
Ts c L 2 d i L
Hold Time of SDI2 Data Input
to SCK2 Edge
30 — — ns
SP50 TssL2scH,
TssL2scL
SS2
 to SCK2  or SCK2 
Input
120 — — ns
SP51 TssH2doZ SS2
 to SDO2 Output
High-Impedance
10 — 50 ns (Note 4)
SP52 TscH2ssH
TscL2ssH
SS2 after SCK2 Edge 1.5 TCY + 40 — — ns (Note 4)
SP60 TssL2doV SDO2 Data Output Valid after
SS2
Edge
— — 50 ns
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI2 pins.